LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 329

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 281. Interrupt Register (TMR16B0IR - address 0x4000 C000 and TMR16B1IR - address 0x4001 0000) bit
UM10398
User manual
Bit
0
1
2
3
4
31:5
description
Symbol
MR0 Interrupt
MR1 Interrupt
MR2 Interrupt
MR3 Interrupt
CR0 Interrupt
-
18.7.2 Timer Control Register (TMR16B0TCR and TMR16B1TCR)
18.7.3 Timer Counter (TMR16B0TC - address 0x4000 C008 and
18.7.4 Prescale Register (TMR16B0PR - address 0x4000 C00C and
The Timer Control Register (TCR) is used to control the operation of the counter/timer.
Table 282. Timer Control Register (TMR16B0TCR - address 0x4000 C004 and TMR16B1TCR -
TMR16B1TC - address 0x4001 0008)
The 16-bit Timer Counter is incremented when the Prescale Counter reaches its terminal
count. Unless it is reset before reaching its upper limit, the TC will count up through the
value 0x0000 FFFF and then wrap back to the value 0x0000 0000. This event does not
cause an interrupt, but a Match register can be used to detect an overflow if needed.
Table 283: Timer counter registers (TMR16B0TC, address 0x4000 C008 and TMR16B1TC
TMR16B1PR - address 0x4001 000C)
The 16-bit Prescale Register specifies the maximum value for the Prescale Counter.
Bit
0
1
31:2
Bit
15:0
31:16
Description
Interrupt flag for match channel 0.
Interrupt flag for match channel 1.
Interrupt flag for match channel 2.
Interrupt flag for match channel 3.
Interrupt flag for capture channel 0 event.
Reserved
Symbol
CEn
CRst
-
Symbol
TC
-
address 0x4001 0004) bit description
0x4001 0008) bit description
Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Description
Timer counter value.
Reserved.
Description
Counter Enable. When one, the Timer Counter and
Prescale Counter are enabled for counting. When zero,
the counters are disabled.
Counter Reset. When one, the Timer Counter and the
Prescale Counter are synchronously reset on the next
positive edge of PCLK. The counters remain reset until
TCR[1] is returned to zero.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
UM10398
© NXP B.V. 2012. All rights reserved.
Reset value
0
0
0
0
0
-
Reset value
0
0
NA
329 of 538
Reset
value
0
-