LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 57

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
5.4 Definitions
5.5 Clocking routine
UM10398
User manual
Fig 12. LPC111x/102/202/302 clock configuration for power API use
wdt_osc_clk
sys_osc_clk
irc_osc_clk
irc_osc_clk
SYSPLLCLKSEL
5.5.1 set_pll
sys_pllclkin
The following elements have to be defined in an application that uses the power profiles:
typedef struct _PWRD {
} PWRD;
typedef struct _ROM {
} ROM;
ROM ** rom = (ROM **) (0x1FFF1FF8 + 3 * sizeof(ROM**));
unsigned int command[4], result[2];
This routine sets up the system PLL according to the calling arguments. If the expected
clock can be obtained by simply dividing the system PLL input, set_pll bypasses the PLL
to lower system power consumption.
Remark: Before this routine is invoked, the PLL clock source (IRC/system oscillator) must
be selected
PLL
set_pll attempts to find a PLL setup that matches the calling parameters. Once a
combination of a feedback divider value (SYSPLLCTRL, M), a post divider ratio
(SYSPLLCTRL, P) and the system/AHB clock divider (SYSAHBCLKDIV) is found, set_pll
applies the selected values and switches the main clock source selection to the system
PLL clock out (if necessary).
(Table
void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
void (*set_power)(unsigned int cmd[], unsigned int resp[]);
const PWRD * pWRD;
MAINCLKSEL
sys_pllclkout
SYS PLL
18) and the system/AHB clock divider must be set to 1
(Table
All information provided in this document is subject to legal disclaimers.
16), the main clock source must be set to the input clock to the system
Rev. 12 — 24 September 2012
7
main clock
SYSAHBCLKDIV
DIVIDER
CLOCK
DIVIDER
CLOCK
Chapter 5: LPC111x/LPC11Cxx Power profiles
SYSAHBCLKCTRL[18]
(SPI1 enable)
system clock
Peripherals
SYSAHBCLKCTRL[1]
(ROM enable)
(Table
UM10398
© NXP B.V. 2012. All rights reserved.
CORTEX-M0
20).
ROM
ARM
SPI1
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