LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 257

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
15.10.3 Slave Receiver mode
In the slave receiver mode, a number of data bytes are received from a master transmitter
(see
follows:
Table 237. I2C0ADR and I2C1ADR usage in Slave Receiver mode
The upper 7 bits are the address to which the I
master. If the LSB (GC) is set, the I
(0x00); otherwise it ignores the General Call address.
Table 238. I2C0CONSET and I2C1CONSET used to initialize Slave Receiver mode
The I
to logic 1 to enable the I
acknowledge its own slave address or the General Call address. STA, STO, and SI must
be reset.
When ADR and CON have been initialized, the I
own slave address followed by the data direction bit which must be “0” (W) for the I
block to operate in the slave receiver mode. After its own slave address and the W bit
have been received, the serial interrupt flag (SI) is set and a valid status code can be read
from STAT. This status code is used to vector to a state service routine. The appropriate
action to be taken for each of these status codes is detailed in
receiver mode may also be entered if arbitration is lost while the I
mode (see status 0x68 and 0x78).
If the AA bit is reset during a transfer, the I
to SDA after the next received data byte. While AA is reset, the I
respond to its own slave address or a General Call address. However, the I
monitored and address recognition may be resumed at any time by setting AA. This
means that the AA bit may be used to temporarily isolate the I
Bit
Symbol
Bit
Symbol
Value
Figure
2
C-bus rate settings do not affect the I
7
7
-
-
55). To initiate the slave receiver mode, ADR and CON must be loaded as
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
6
6
I2EN
1
2
C block. The AA bit must be set to enable the I
5
5
STA
0
own slave 7-bit address
2
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
C block will respond to the General Call address
4
4
STO
0
2
C block will return a not acknowledge (logic 1)
2
C block in the slave mode. I2EN must be set
2
C block will respond when addressed by a
2
C block waits until it is addressed by its
3
3
SI
0
2
2
AA
1
2
Table
C block from the I
2
2
C block does not
C block is in the master
239. The slave
UM10398
1
1
-
-
© NXP B.V. 2012. All rights reserved.
2
C block to
2
C-bus is still
0
GC
0
-
-
2
257 of 538
C-bus.
2
C