LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 305

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
16.7.3.5 Receive/transmit priority
16.7.3.6 Configuration of a transmit object
16.7.3.7 Updating a transmit object
The receive/transmit priority for the Message Objects is attached to the message number.
Message Object 1 has the highest priority, while Message Object 32 has the lowest
priority. If more than one transmission request is pending, they are serviced due to the
priority of the corresponding Message Object.
Table 275
Table
Table 275. Initialization of a transmit object
The Arbitration Registers (ID28:0 and XTD bit) are given by the application. They define
the identifier and the type of the outgoing message. If an 11-bit Identifier (“Standard
Frame”) is used, it is programmed to ID28. In this case ID18, ID17 to ID0 can be
disregarded.
If the TXIE bit is set, the INTPND bit will be set after a successful transmission of the
Message Object.
If the RMTEN bit is set, a matching received Remote Frame will cause the TXRQST bit to
be set, and the Remote Frame will autonomously be answered by a Data Frame.
The Data Registers (DLC3:0, Data0:7) are given by the application. TXRQST and RMTEN
may not be set before the data is valid.
The Mask Registers (Msk28-0, UMASK, MXTD, and MDIR bits) may be used
(UMASK=’1’) to allow groups of Remote Frames with similar identifiers to set the TXRQST
bit. For details see
The CPU may update the data bytes of a Transmit Object any time via the IFx Interface
registers. Neither MSGVAL nor TXRQST have to be reset before the update.
Even if only a part of the data bytes are to be updated, all four bytes of the corresponding
IFx Data A Register or IFx Data B Register have to be valid before the content of that
register is transferred to the Message Object. Either the CPU has to write all four bytes
into the IFx Data Register or the Message Object is transferred to the IFx Data Register
before the CPU writes the new data bytes.
When only the (eight) data bytes are updated, first 0x0087 is written to the Command
Mask Register. Then the number of the Message Object is written to the Command
Request Register, concurrently updating the data bytes and setting TXRQST.
MSGVAL
MSGLST
1
0
253):
shows how a transmit object should be initialized by software (see also
Arbitration
application
dependent
All information provided in this document is subject to legal disclaimers.
RXIE
bits
0
Section
Rev. 12 — 24 September 2012
application
dependent
application
dependent
16.7.3.4.2. The DIR bit should not be masked.
Data bits
TXIE
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
application
dependent
Mask bits
INTPND
0
application
dependent
RMTEN
EOB
1
DIR
1
UM10398
© NXP B.V. 2012. All rights reserved.
TXRQST
0
NEWDAT
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0