LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 458

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.4.3.3 Exception handlers
28.4.3.4 Vector table
Table 427. Properties of different exception types
[1]
[2]
[3]
[4]
For an asynchronous exception, other than reset, the processor can execute additional
instructions between when the exception is triggered and when the processor enters the
exception handler.
Privileged software can disable the exceptions that
configurable priority, see
For more information about HardFaults, see
The processor handles exceptions using:
Interrupt Service Routines (ISRs) — Interrupts IRQ0 to IRQ31 are the exceptions
handled by ISRs.
Fault handler — HardFault is the only exception handled by the fault handler.
System handlers — NMI, PendSV, SVCall SysTick, and HardFault are all system
exceptions handled by system handlers.
The vector table contains the reset value of the stack pointer, and the start addresses,
also called exception vectors, for all exception handlers.
of the exception vectors in the vector table. The least-significant bit of each vector must be
1, indicating that the exception handler is written in Thumb code.
Exception
number
12-13
14
15
16 and above
To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for
exceptions other than interrupts. The IPSR returns the Exception number, see
See
See
Increasing in steps of 4.
Section 28.4.3.4
Section
[1]
28–28.6.2.6.
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
IRQ
number
-
-2
-1
0 and above
Rev. 12 — 24 September 2012
for more information.
Section
[1]
28–28.6.2.3.
Exception
type
Reserved
PendSV
SysTick
Interrupt (IRQ)
Section
Table 28–427
28–28.4.4.
Priority
-
Configurable
Configurable
Configurable
Figure 28–100
shows as having
[3]
[3]
[3]
Table
UM10398
© NXP B.V. 2012. All rights reserved.
28–422.
shows the order
-
Vector
address
0x00000038
0x0000003C
0x00000040 and
above
[4]
[2]
458 of 538