C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet

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C8051F581-IMR

Manufacturer Part Number
C8051F581-IMR
Description
8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F581-IMR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Rev. 1.2 4/11
Analog Peripherals
-
-
On-Chip Debug
-
-
-
-
Supply Voltage 1.8 to 5.25 V
-
High-Speed 8051 µC Core
-
-
-
Automotive Qualified
-
12-Bit ADC
Three Comparators
On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping, 
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Low cost, complete development kit
Typical operating current: 15 mA at 50 MHz;
Typical stop mode current: 230 µA
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
Up to 50 MIPS throughput with 50 MHz clock
Expanded interrupt handler
Temperature Range: –40 to +125 °C
Up to 200 ksps
Up to 32 external single-ended inputs
VREF from on-chip VREF, external pin or V
Internal or external start of conversion source
Built-in temperature sensor
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current
Comparators 0-2
M
A
U
X
INTERRUPTS
INTERNAL OSCILLATOR
ISP FLASH
FLEXIBLE
PERIPHERALS
24 MHz PRECISION
128 kB
12-bit
200 ksps
ADC
Voltage
ANALOG
HIGH-SPEED CONTROLLER CORE
Copyright © 2011 by Silicon Laboratories
DD
SENSOR
VREG
TEMP
VREF
CIRCUITRY
8051 CPU
(50 MIPS)
DEBUG
Memory
-
-
-
Digital Peripherals
-
-
-
-
-
-
Clock Sources
-
-
-
Packages
-
-
-
Timers 0-5
UART 0-1
PCA x 2
SMBus
CAN
SPI
LIN
2x Clock Multiplier
8448 bytes internal data RAM (256 + 8192 XRAM)
128 or 96 kB Banked Flash; In-system programma-
ble in 512-byte Sectors
External 64 kB data memory interface programma-
ble for multiplexed or non-multiplexed mode
40, 33, or 25 Port I/O; All 5 V push-pull with high
sink current
CAN 2.0 Controller—no crystal required
LIN 2.1 Controller (Master and Slave capable); no
crystal required
Two Hardware enhanced UARTs, SMBus™, and
enhanced SPI™ serial ports
Six general purpose 16-bit counter/timers
Two 16-Bit programmable counter array (PCA)
peripherals with six capture/compare modules each
and enhanced PWM functionality
Internal 24 MHz with ±0.5% accuracy for CAN and
master LIN operation.
External oscillator: Crystal, RC, C, or clock 
(1 or 2 pin modes)
Can switch between clock sources on-the-fly; 
useful in power saving modes
48-Pin QFP/QFN (C8051F580/1/4/5)
40-Pin QFN (C8051F588/9-F590/1)
32-Pin QFP/QFN (C8051F582/3/6/7)
DIGITAL I/O
Mixed Signal ISP Flash MCU Family
POR
8 kB XRAM
Ports 0-4
Crossbar
Interface
External
Memory
C8051F58x/F59x
WDT
C8051F580/1/2/3/4/5/6/7/8/9-F590/1

Related parts for C8051F581-IMR

C8051F581-IMR Summary of contents

Page 1

Analog Peripherals - 12-Bit ADC Up to 200 ksps • external single-ended inputs • VREF from on-chip VREF, external pin or V • Internal or external start of conversion source • Built-in temperature sensor • - Three ...

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C8051F58x/F59x 2 Rev. 1.2 ...

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Table of Contents 1. System Overview ..................................................................................................... 18 2. Ordering Information ............................................................................................... 22 3. Pin Definitions.......................................................................................................... 24 4. Package Specifications ........................................................................................... 32 4.1. QFP-48 Package Specifications........................................................................ 32 4.2. QFN-48 Package Specifications........................................................................ 34 4.3. QFN-40 Package Specifications........................................................................ 36 4.4. QFP-32 Package ...

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C8051F58x/F59x 12.2.1.2. Bit Addressable Locations ............................................................ 105 12.2.1.3. Stack .......................................................................................... 105 13. Special Function Registers................................................................................. 106 13.1. SFR Paging ................................................................................................... 106 13.2. Interrupts and SFR Paging ............................................................................ 106 13.3. SFR Page Stack Example ............................................................................. 107 14. Interrupts .............................................................................................................. 126 14.1. ...

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Non-multiplexed Configuration.............................................................. 163 18.5. Memory Mode Selection................................................................................ 164 18.5.1. Internal XRAM Only .............................................................................. 164 18.5.2. Split Mode without Bank Select............................................................. 164 18.5.3. Split Mode with Bank Select.................................................................. 165 18.5.4. External Only......................................................................................... 165 18.6. Timing .......................................................................................................... 165 18.6.1. Non-Multiplexed Mode ...

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C8051F58x/F59x 21.4. LIN Slave Mode Operation ............................................................................ 217 21.5. Sleep Mode and Wake-Up ............................................................................ 218 21.6. Error Detection and Handling ........................................................................ 218 21.7. LIN Registers................................................................................................. 219 21.7.1. LIN Direct Access SFR Registers Definitions ....................................... 219 21.7.2. LIN Indirect Access SFR ...

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UART ............................................................................................ 265 25.2.2. 9-Bit UART ............................................................................................ 265 25.3. Multiprocessor Communications ................................................................... 266 26. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 270 26.1. Signal Descriptions........................................................................................ 271 26.1.1. Master Out, Slave In (MOSI)................................................................. 271 26.1.2. Master In, Slave Out (MISO)................................................................. ...

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C8051F58x/F59x 28.4. Watchdog Timer Mode .................................................................................. 322 28.4.1. Watchdog Timer Operation ................................................................... 322 28.4.2. Watchdog Timer Usage ........................................................................ 323 28.5. Register Descriptions for PCA0..................................................................... 325 29. Programmable Counter Array 1 (PCA1)............................................................. 331 29.1. PCA1 Counter/Timer ..................................................................................... 332 29.2. PCA1 Interrupt ...

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List of Figures Figure 1.1. C8051F580/1/4/5 Block Diagram .......................................................... 19 Figure 1.2. C8051F588/9-F590/1 Block Diagram .................................................... 20 Figure 1.3. C8051F582/3/6/7 Block Diagram .......................................................... 21 Figure 3.1. QFP-48 Pinout Diagram (Top View) ...................................................... 27 Figure 3.2. QFN-48 Pinout Diagram (Top View) ...

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C8051F58x/F59x Figure 13.4. SFR Page Stack Upon PCA Interrupt Occurring During a CAN0 ISR 110 Figure 13.5. SFR Page Stack Upon Return From PCA Interrupt .......................... 111 Figure 13.6. SFR Page Stack Upon Return From CAN0 Interrupt ........................ 112 Figure ...

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Figure 27.2. T0 Mode 2 Block Diagram ................................................................. 287 Figure 27.3. T0 Mode 3 Block Diagram ................................................................. 288 Figure 27.4. Timer 2 16-Bit Mode Block Diagram ................................................. 293 Figure 27.5. Timer 2 8-Bit Mode Block Diagram ................................................... 294 Figure 27.6. ...

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C8051F58x/F59x List of Tables Table 2.1. Product Selection Guide ......................................................................... 23 Table 3.1. Pin Definitions for the C8051F58x/F59x ................................................. 24 Table 4.1. QFP-48 Package Dimensions ................................................................ 32 Table 4.2. QFP-48 Landing Diagram Dimensions ................................................... 33 Table 4.3. QFN-48 Package Dimensions ...

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Table 23.1. SMBus Clock Source Selection .......................................................... 241 Table 23.2. Minimum SDA Setup and Hold Times ................................................ 242 Table 23.3. Sources for Hardware Changes to SMB0CN ..................................... 246 Table 23.4. SMBus Status Decoding ..................................................................... 252 Table 24.1. Baud Rate Generator ...

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C8051F58x/F59x List of Registers SFR Definition 6.4. ADC0CF: ADC0 Configuration ...................................................... 65 SFR Definition 6.5. ADC0H: ADC0 Data Word MSB .................................................... 66 SFR Definition 6.6. ADC0L: ADC0 Data Word LSB ...................................................... 66 SFR Definition 6.7. ADC0CN: ADC0 Control ................................................................ 67 ...

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SFR Definition 15.4. CCH0CN: Cache Control ........................................................... 146 SFR Definition 15.5. ONESHOT: Flash Oneshot Period ............................................ 146 SFR Definition 16.1. PCON: Power Control ................................................................ 149 SFR Definition 17.1. VDM0CN: VDD Monitor Control ................................................ 153 SFR Definition 17.2. RSTSRC: Reset Source ...

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C8051F58x/F59x SFR Definition 21.2. LIN0DAT: LIN0 Indirect Data Register ....................................... 219 SFR Definition 21.3. LIN0CF: LIN0 Control Mode Register ........................................ 220 SFR Definition 22.1. CAN0CFG: CAN Clock Configuration ........................................ 236 SFR Definition 23.1. SMB0CF: SMBus Clock/Configuration ...................................... 243 SFR Definition ...

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SFR Definition 28.5. PCA0L: PCA0 Counter/Timer Low Byte .................................... 329 SFR Definition 28.6. PCA0H: PCA0 Counter/Timer High Byte ................................... 329 SFR Definition 28.7. PCA0CPLn: PCA0 Capture Module Low Byte ........................... 330 SFR Definition 28.8. PCA0CPHn: PCA0 Capture Module High Byte ...

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... User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands ...

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Power On CIP-51 8051 Reset Controller Core Reset 128 Flash Program Memory Debug / C2CK/RST Programming Hardware 256 Byte RAM C2D 8 kB XRAM Voltage Regulator VREGIN (LDO) VDD GND System Clock Setup XTAL1 Internal Oscillator External ...

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C8051F58x/F59x Power On CIP-51 8051 Reset Controller Core Reset 128 Flash Program Memory Debug / C2CK/RST Programming 256 Byte RAM Hardware C2D 8 kB XRAM Voltage Regulator VREGIN (LDO) VDD GND System Clock Setup XTAL1 Internal Oscillator ...

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Power On CIP-51 8051 Reset Controller Core Reset 128 Flash Program Memory Debug / C2CK/RST Programming Hardware 256 Byte RAM C2D 8 kB XRAM Voltage Regulator VREGIN (LDO) VDD GND System Clock Setup XTAL1 XTAL2 Internal Oscillator ...

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C8051F58x/F59x 2. Ordering Information The following features are common to all devices in this family:  50 MHz system clock and 50 MIPS throughput (peak)  8448 bytes of RAM (256 internal bytes and 8192 XRAM bytes 2  SMBus/I ...

Page 23

... Table 2.1. Product Selection Guide   C8051F580-IQ 128   C8051F580-IM 128 C8051F581-IQ 128 — — 40 C8051F581-IM 128 — — 40   C8051F582-IQ 128   C8051F582-IM 128 C8051F583-IQ 128 — — 25 — QFP-32 C8051F588-IM 128 C8051F583-IM 128 — — 25 — QFN-32 C8051F589-IM 128 — — 33  ...

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C8051F58x/F59x 3. Pin Definitions Table 3.1. Pin Definitions for the C8051F58x/F59x Name Pin Pin F580/1/4/5 F588/9- F590/1 (40-pin) (48-pin) VDD 4 4 GND 6 6 VDDA 5 5 GNDA 7 7 VREGIN 3 3 VIO 2 2 RST ...

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Table 3.1. Pin Definitions for the C8051F58x/F59x (Continued) Name Pin Pin F580/1/4/5 F588/9- F582/3/6/7 F590/1 (40-pin) (48-pin P1.5 37 ...

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C8051F58x/F59x Table 3.1. Pin Definitions for the C8051F58x/F59x (Continued) Name Pin Pin F580/1/4/5 F588/9- F590/1 (40-pin) (48-pin) P3 P4.0 18 — P4.1 17 — P4.2 16 — P4.3 15 — P4.4 14 — P4.5 13 — P4.6 10 ...

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... P0.1 / CNVSTR 1 VIO 2 VREGIN 3 VDD 4 VDDA 5 GND 6 GNDA 7 P0.0 / VREF 8 P4.7 9 P4.6 10 C2D 11 RST / C2CK 12 Figure 3.1. QFP-48 Pinout Diagram (Top View) C8051F58x/F59x C8051F580-IQ C8051F581-IQ C8051F584-IQ C8051F585-IQ Top View Rev. 1.2 P1.6 36 P1.7 35 P2.0 34 P2.1 33 P2.2 32 P2.3 31 P2.4 30 P2.5 29 P2.6 28 P2.7 27 P3 ...

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... C8051F58x/F59x P0.1 / CNVSTR 1 VIO 2 VREGIN 3 VDD 4 VDDA 5 GND 6 GNDA 7 P0.0 / VREF 8 P4.7 9 P4.6 10 C2D 11 RST/C2CK 12 Figure 3.2. QFN-48 Pinout Diagram (Top View) 28 C8051F580-IM C8051F581-IM C8051F584-IM C8051F585-IM Top View GND Rev. 1.2 36 P1.6 35 P1.7 34 P2.0 33 P2.1 32 P2.2 31 P2.3 30 P2.4 29 P2.5 28 P2.6 27 P2.7 26 P3.0 25 P3.1 ...

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P0.1 / CNVSTR 1 VIO 2 VREGIN 3 VDD 4 VDDA 5 GND 6 GNDA 7 P0.0 / VREF 8 P4.0 / C2D 9 RST / C2CK 10 Figure 3.3. QFN-40 Pinout Diagram (Top View) C8051F58x/F59x C8051F588-IM C8051F589-IM C8051F590-IM C8051F591-IM ...

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C8051F58x/F59x 1 P0.1 / CNVSTR VIO 2 VREGIN 3 VDD 4 VDDA 5 6 GND 7 GNDA 8 P0.0 / VREF Figure 3.4. QFP-32 Pinout Diagram (Top View) 30 C8051F582-IQ C8051F583-IQ C8051F586-IQ C8051F587-IQ Top View Rev. 1.2 24 P1.2 23 ...

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P0.1 / CNVSTR 1 VIO 2 VREGIN 3 VDD 4 VDDA 5 GND 6 GNDA 7 P0.0 / VREF 8 Figure 3.5. QFN-32 Pinout Diagram (Top View) C8051F58x/F59x C8051F582-IM C8051F583-IM C8051F586-IM C8051F587-IM Top View GND Rev. 1.2 24 P1.2 23 ...

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C8051F58x/F59x 4. Package Specifications 4.1. QFP-48 Package Specifications Figure 4.1. QFP-48 Package Drawing Table 4.1. QFP-48 Package Dimensions Dimension Min Typ A — — A1 0.05 — A2 0.95 1.00 b 0.17 0.22 c 0.09 — D 9.00 BSC. D1 ...

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Figure 4.2. QFP-48 Landing Diagram Table 4.2. QFP-48 Landing Diagram Dimensions Dimension Min C1 8.30 C2 8.30 E 0.50 BSC Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based ...

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C8051F58x/F59x 4.2. QFN-48 Package Specifications Figure 4.3. QFN-48 Package Drawing Table 4.3. QFN-48 Package Dimensions Dimension Min Typ A 0.80 0. 0.18 0.23 D 7.00 BSC D2 3.90 4.00 e 0.50 BSC E 7.00 BSC Notes: ...

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Figure 4.4. QFN-48 Landing Diagram Table 4.4. QFN-48 Landing Diagram Dimensions Dimension Min C1 6.80 C2 6.80 e 0.50 BSC X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimension and Tolerancing is ...

Page 36

C8051F58x/F59x 4.3. QFN-40 Package Specifications Figure 4.5. Typical QFN-40 Package Drawing Table 4.5. QFN-40 Package Dimensions Dimension Min Typ A 0.80 0.85 A1 0.00 b 0.18 0.23 D 6.00 BSC D2 4.00 4.10 e 0.50 BSC E 6.00 BSC Notes: ...

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Figure 4.6. QFN-40 Landing Diagram Table 4.6. QFN-40 Landing Diagram Dimensions Dimension Min C1 5.80 C2 5.80 e 0.50 BSC X1 0.15 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimension and Tolerancing is ...

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C8051F58x/F59x 4.4. QFP-32 Package Specifications Figure 4.7. QFP-32 Package Drawing Table 4.7. QFP-32 Package Dimensions Dimension Min Typ A — — A1 0.05 — A2 1.35 1.40 b 0.30 0.37 c 0.09 — D 9.00 BSC. D1 7.00 BSC. e ...

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Figure 4.8. QFP-32 Package Drawing Table 4.8. QFP-32 Landing Diagram Dimensions Dimension Min C1 8.40 C2 8.40 E 0.80 BSC Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based ...

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C8051F58x/F59x 4.5. QFN-32 Package Specifications Figure 4.9. QFN-32 Package Drawing Table 4.9. QFN-32 Package Dimensions Dimension Min Typ A 0.80 0.9 A1 0.00 0.02 b 0.18 0.25 D 5.00 BSC. D2 3.20 3.30 e 0.50 BSC. E 5.00 BSC. Notes: ...

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Figure 4.10. QFN-32 Package Drawing Table 4.10. QFN-32 Landing Diagram Dimensions Dimension Min C1 4.80 C2 4.80 e 0.50 BSC X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design ...

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C8051F58x/F59x 5. Electrical Characteristics 5.1. Absolute Maximum Specifications Table 5.1. Absolute Maximum Ratings Parameter Ambient Temperature under Bias Storage Temperature Voltage on V with Respect to GND REGIN Voltage on V with Respect to GND DD Voltage on VDDA with ...

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Electrical Characteristics Table 5.2. Global Electrical Characteristics –40 to +125 °C, 24 MHz system clock unless otherwise specified. Parameter Supply Input Voltage (V ) REGIN Digital Supply Voltage (V ) System Clock < 25 MHz DD System Clock > ...

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C8051F58x/F59x Table 5.2. Global Electrical Characteristics (Continued) –40 to +125 °C, 24 MHz system clock unless otherwise specified. Parameter MHz I Supply Sensitivity DD F ...

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Table 5.2. Global Electrical Characteristics (Continued) –40 to +125 °C, 24 MHz system clock unless otherwise specified. Parameter Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash ...

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C8051F58x/F59x Figure 5.1. Maximum System Clock Frequency vs. VDD Voltage Note: With system clock frequencies greater than 25 MHz, the V (VDMLVL = 1b in SFR VDM0CN) to prevent undefined CPU operation. The high threshold should only be used with ...

Page 47

Table 5.3. Port I/O DC Electrical Characteristics V = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified. DD Parameters Output High Voltage I = –3 mA, Port I/O push-pull –10 µA, Port I/O push-pull ...

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C8051F58x/F59x Table 5.4. Reset Electrical Characteristics –40 to +125 °C unless otherwise specified. Parameter RST Output Low Voltage RST Input High Voltage RST Input Low Voltage RST Input Pullup Current V POR Threshold ( RST-LOW V POR Threshold ...

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Table 5.6. Internal High-Frequency Oscillator Electrical Characteristics V = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified; Using factory-calibrated settings. DD Parameter Oscillator Frequency IFCN = 111b; VDD > VREGMIN IFCN = 111b; VDD < VREGMIN Oscillator ...

Page 50

C8051F58x/F59x Table 5.7. Clock Multiplier Electrical Specifications V = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified. DD Parameter Input Frequency (Fcm ) in Output Frequency Power Supply Current Table 5.8. Voltage Regulator Electrical Characteristics V = ...

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Table 5.9. ADC0 Electrical Characteristics VDDA = 1.8 to 2.75 V, –40 to +125 °C, VREF = 1.5 V (REFSL=0) unless otherwise specified. Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic 1 Offset Error Full Scale Error Offset ...

Page 52

C8051F58x/F59x Table 5.10. Temperature Sensor Electrical Characteristics VDDA = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified. Parameter Linearity Slope Slope Error* Offset Offset Error* Power Supply Current Tracking Time *Note: Represents one standard deviation from the ...

Page 53

Table 5.12. Comparator 0, 1 and 2 Electrical Characteristics VIO = 1.8 to 5.25 V, –40 to +125 °C unless otherwise noted. Parameter CPn+ – CPn– = 100 mV Response Time: * Mode 0, Vcm = 1.5 V CPn+ – ...

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C8051F58x/F59x 6. 12-Bit ADC (ADC0) The ADC0 on the C8051F58x/F59x consists of an analog multiplexer (AMUX0) with 35/28 total input selec- tions and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, programmable window detector, programmable attenuation (1:2), and ...

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Modes of Operation In a typical system, ADC0 is configured using the following steps gain adjustment is required, refer to Section “6.3. Selectable Gain” on page 60. 2. Choose the start of conversion source. 3. Choose ...

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C8051F58x/F59x Post-Tracking Mode is selected when AD0TM is set to 01b. A programmable tracking time based on AD0TK is started immediately following the convert start signal. Conversions are started after the pro- grammed tracking time ends. After a conversion is ...

Page 57

Convert Start Time F S1 ADC0 State AD0INT Flag Post-Tracking or Dual-Tracking Modes (AD0TK = ‘00') Time F S1 ADC0 State Track AD0INT Flag Key F Sn Figure 6.3. 12-Bit ADC Tracking Mode Example 6.1.4. Burst Mode Burst Mode is ...

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C8051F58x/F59x been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and less-than registers until “repeat count” conversions have been accumulated. Note: When using Burst Mode, care must be taken to issue a convert start signal ...

Page 59

Output Code Formatting The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code. When the repeat count is set to 1, conversion codes are represented in 12-bit unsigned integer format and the output ...

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C8051F58x/F59x Px.x Figure 6.5. ADC0 Equivalent Input Circuit 6.3. Selectable Gain ADC0 on the C8051F58x/F59x family of devices implements a selectable gain adjustment option. By writ- ing a value to the gain adjust address range, the user can select gain ...

Page 61

For example, if ADC0GNH = 0xFC, ADC0GNL = 0x00, and GAINADD = 1, GAIN = 0xFC0 = 4032, and the resulting equation is as follows:  4032 ------------ - GAIN =  4096 The table below equates values in the ...

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C8051F58x/F59x 6.3.2. Setting the Gain Value The three programmable gain registers are accessed indirectly using the ADC0H and ADC0L registers when the GAINEN bit (ADC0CF.0) bit is set. ADC0H acts as the address register, and ADC0L is the data register. ...

Page 63

Gain Register Definition 6.1. ADC0GNH: ADC0 Selectable Gain High Byte Bit 7 6 Name Type 1 1 Reset Indirect Address = 0x04; Bit Name 7:0 GAINH[7:0] ADC0 Gain High Byte. See Section 6.3.1 for details on calculating the value for ...

Page 64

C8051F58x/F59x Gain Register Definition 6.3. ADC0GNA: ADC0 Additional Selectable Gain Bit 7 6 Name Reserved Reserved Reserved W W Type 0 0 Reset Indirect Address = 0x08; Bit Name 7:1 Reserved Reserved. Must Write 0000000b. 0 GAINADD ADC0 Additional Gain ...

Page 65

SFR Definition 6.4. ADC0CF: ADC0 Configuration Bit 7 6 AD0SC[4:0] Name Type 1 1 Reset SFR Address = 0xBC; SFR Page = 0x00 Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system ...

Page 66

C8051F58x/F59x SFR Definition 6.5. ADC0H: ADC0 Data Word MSB Bit 7 6 Name Type 0 0 Reset SFR Address = 0xBE; SFR Page = 0x00 Bit Name 7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits. For AD0LJST = 0 and AD0RPT ...

Page 67

SFR Definition 6.7. ADC0CN: ADC0 Control Bit 7 6 AD0EN BURSTEN AD0INT Name R/W R/W Type 0 0 Reset SFR Address = 0xE8; SFR Page = 0x00; Bit-Addressable Bit Name 7 AD0EN ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is ...

Page 68

C8051F58x/F59x SFR Definition 6.8. ADC0TK: ADC0 Tracking Mode Select Bit 7 6 AD0PWR[3:0] Name R/W Type 1 1 Reset SFR Address = 0xBA; SFR Page = 0x00; Bit Name 7:4 AD0PWR[3:0] ADC0 Burst Power-Up Time. For BURSTEN = 0: ADC0 ...

Page 69

SFR Definition 6.9. ADC0GTH: ADC0 Greater-Than Data High Byte Bit 7 6 Name Type 1 1 Reset SFR Address = 0xC4; SFR Page = 0x00 Bit Name 7:0 ADC0GTH[7:0] ADC0 Greater-Than Data Word High-Order Bits. SFR Definition 6.10. ADC0GTL: ADC0 ...

Page 70

C8051F58x/F59x SFR Definition 6.11. ADC0LTH: ADC0 Less-Than Data High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xC6; SFR Page = 0x00 Bit Name 7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. SFR Definition 6.12. ADC0LTL: ...

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ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (4095/4096) 0x0FFF AD0WINT not affected 0x0201 VREF x (512/4096) 0x0200 ADC0LTH:ADC0LTL 0x01FF 0x0101 VREF x (256/4096) 0x0100 ADC0GTH:ADC0GTL 0x00FF AD0WINT not affected 0x0000 0 Figure 6.6. ADC Window Compare Example: Right-Justified Data ...

Page 72

C8051F58x/F59x 6.5. ADC0 Analog Multiplexer ADC0 includes an analog multiplexer to enable multiple analog input sources. Any of the following may be selected as an input: P0.0–P3.7, the on-chip temperature sensor, the core power supply (V (GND). ADC0 is single-ended ...

Page 73

SFR Definition 6.13. ADC0MX: ADC0 Channel Select Bit 7 6 Name Type R R Reset 0 0 SFR Address = 0xBB; SFR Page = 0x00; Bit Name 7:6 Unused Read = 00b; Write = Don’t Care. 5:0 AMX0P[5:0] AMUX0 Positive ...

Page 74

C8051F58x/F59x 7. Temperature Sensor An on-chip temperature sensor is included on the C8051F58x/F59x devices which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the tempera- ture sensor, the ADC multiplexer channel ...

Page 75

Voltage Reference The Voltage reference multiplexer on the C8051F58x/F59x devices is configurable to use an externally connected voltage reference, the on-chip reference voltage generator routed to the VREF pin, or the V power supply voltage (see Figure 8.1). The ...

Page 76

C8051F58x/F59x SFR Definition 8.1. REF0CN: Reference Control Bit 7 6 ZTCEN Name R R Type 0 0 Reset SFR Address = 0xD1; SFR Page = 0x00 Bit Name 7:6 Unused Read = 00b; Write = don’t care. 5 ZTCEN Zero ...

Page 77

Comparators The C8051F58x/F59x devices include three on-chip programmable voltage Comparators. A block diagram of the comparators is shown in Figure 9.1, where “n” is the comparator number ( 2). The three Com- parators operate identically except that ...

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C8051F58x/F59x Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system clock; the asynchronous output is ...

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Note that false rising edges and falling edges can be detected when the comparator is first powered changes are made to the hysteresis or response time control bits. Therefore recommended that the rising-edge and falling-edge ...

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C8051F58x/F59x SFR Definition 9.2. CPT0MD: Comparator0 Mode Selection Bit 7 6 CP0RIE Name R R Type 0 0 Reset SFR Address = 0x9B; SFR Page = 0x00 Bit Name 7:6 Unused Read = 00b, Write = Don’t Care. 5 CP0RIE ...

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SFR Definition 9.3. CPT1CN: Comparator1 Control Bit 7 6 CP1EN CP1OUT CP1RIF Name R/W R Type 0 0 Reset SFR Address = 0x9D; SFR Page = 0x00 Bit Name 7 CP1EN Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. ...

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C8051F58x/F59x SFR Definition 9.4. CPT1MD: Comparator1 Mode Selection Bit 7 6 CP1RIE Name R R Type 0 0 Reset SFR Address = 0x9E; SFR Page = 0x00 Bit Name 7:6 Unused Read = 00b, Write = Don’t Care. 5 CP1RIE ...

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SFR Definition 9.5. CPT2CN: Comparator2 Control Bit 7 6 CP2EN CP2OUT CP2RIF Name R/W R Type 0 0 Reset SFR Address = 0x9A; SFR Page = 0x10 Bit Name 7 CP2EN Comparator2 Enable Bit. 0: Comparator2 Disabled. 1: Comparator2 Enabled. ...

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C8051F58x/F59x SFR Definition 9.6. CPT2MD: Comparator2 Mode Selection Bit 7 6 CP2RIE Name R R Type 0 0 Reset SFR Address = 0x9B; SFR Page = 0x10 Bit Name 7:6 Unused Read = 00b, Write = Don’t Care. 5 CP2RIE ...

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Comparator Multiplexer C8051F58x/F59x devices include an analog input multiplexer for each of the comparators to connect Port I/O pins to the comparator inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Def- inition 9.7). The CMX0P3–CMX0P0 bits ...

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C8051F58x/F59x SFR Definition 9.7. CPT0MX: Comparator0 MUX Selection Bit 7 6 CMX0N[3:0] Name R/W Type 0 1 Reset SFR Address = 0x9C; SFR Page = 0x00 Bit Name 7:4 CMX0N[3:0] Comparator0 Negative Input MUX Selection. 0000: 0001: 0010: 0011: 0100: ...

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SFR Definition 9.8. CPT1MX: Comparator1 MUX Selection Bit 7 6 CMX1N[3:0] Name R/W Type 0 1 Reset SFR Address = 0x9F; SFR Page = 0x00 Bit Name 7:4 CMX1N[3:0] Comparator1 Negative Input MUX Selection. 0000: 0001: 0010: 0011: 0100: 0101: ...

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C8051F58x/F59x SFR Definition 9.9. CPT2MX: Comparator2 MUX Selection Bit 7 6 CMX2N[3:0] Name R/W Type 0 1 Reset SFR Address = 0x9C; SFR Page = 0x10 Bit Name 7:4 CMX2N[3:0] Comparator2 Negative Input MUX Selection. 0000: 0001: 0010: 0011: 0100: ...

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Voltage Regulator (REG0) C8051F58x/F59x devices include an on-chip low dropout voltage regulator (REG0). The input to REG0 at the V pin can be as high as 5.25 V. The output can be selected by software to 2 ...

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C8051F58x/F59x If the internal voltage regulator is not used, the V Figure 10. 4.7 µF Figure 10.2. External Capacitors for Voltage Regulator Input/Output—Regulator Disabled SFR Definition 10.1. REG0CN: Regulator Control Bit 7 6 Name REGDIS Reserved Type R/W ...

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CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...

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... This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or other on-chip resources. C2 details can be found in “C2 Interface” on page 349. The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro- vides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-sys- tem device programming and debugging ...

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Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc- tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary ...

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C8051F58x/F59x Table 11.1. CIP-51 Instruction Set Summary (Prefetch-Enabled) Mnemonic Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to ...

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Table 11.1. CIP-51 Instruction Set Summary (Prefetch-Enabled) (Continued) Mnemonic XRL A, #data Exclusive-OR immediate to A XRL direct, A Exclusive- direct byte XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement A ...

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C8051F58x/F59x Table 11.1. CIP-51 Instruction Set Summary (Prefetch-Enabled) (Continued) Mnemonic SETB C Set Carry SETB bit Set direct bit CPL C Complement Carry CPL bit Complement direct bit ANL C, bit AND direct bit to Carry ANL C, /bit AND ...

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Notes on Registers, Operands and Addressing Modes: Rn—Register R0–R7 of the currently selected register bank. @Ri—Data RAM location addressed indirectly through R0 or R1. rel—8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by ...

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C8051F58x/F59x SFR Definition 11.1. DPL: Data Pointer Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x82; SFR Page = All Pages Bit Name 7:0 DPL[7:0] Data Pointer Low. The DPL register is the low byte ...

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SFR Definition 11.3. SP: Stack Pointer Bit 7 6 Name Type 0 0 Reset SFR Address = 0x81; SFR Page = All Pages Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the ...

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C8051F58x/F59x SFR Definition 11.6. PSW: Program Status Word Bit Name R/W R/W Type 0 0 Reset SFR Address = 0xD0; SFR Page = All Pages; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set ...

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Serial Number Special Function Registers (SFRs) The C8051F58x/F59x devices include four SFRs, SN0 through SN3, that are pre-programmed during pro- duction with a unique, 32-bit serial number. The serial number provides a unique identification number for each device and ...

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C8051F58x/F59x 12. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space ...

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The IFBANK bits select which of the upper banks are used for code execution, while the COBANK bits select the bank to be used for direct writes and reads of the Flash memory. On the C8051F580/1/2/3/8/9 devices, the upper 1024 ...

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C8051F58x/F59x SFR Definition 12.1. PSBANK: Program Space Bank Select Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Address = 0xF5; SFR Page = All Pages Bit Name 7:6 Reserved Read = 00b, Must Write = 00b. 5:4 ...

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Internal RAM There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or ...

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C8051F58x/F59x 13. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the C8051F58x/F59x's resources and peripher- als. The CIP-51 controller core duplicates the ...

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Interrupt Logic CIP-51 Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register (SFR0CN). This function defaults to “enabled” ...

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C8051F58x/F59x 0x0 (SPI0DAT) Figure 13.2. SFR Page Stack While Using SFR Page 0x0 To Access SPI0DAT While CIP-51 executes in-line code (writing values to SPI0DAT in this example), the CAN0 Interrupt occurs. The CIP-51 vectors to the CAN0 ISR and ...

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SFRPAGE pushed to SFRNEXT Figure 13.3. SFR Page Stack After CAN0 Interrupt Occurs While in the CAN0 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority interrupt, while the CAN0 interrupt is configured as ...

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C8051F58x/F59x SFRPAGE pushed to SFRNEXT SFRNEXT pushed to SFRLAST Figure 13.4. SFR Page Stack Upon PCA Interrupt Occurring During a CAN0 ISR On exit from the PCA interrupt service routine, the CIP-51 will return to the CAN0 ISR. On execution ...

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SFRNEXT popped to SFRPAGE SFRLAST popped to SFRNEXT Figure 13.5. SFR Page Stack Upon Return From PCA Interrupt On the execution of the RETI instruction in the CAN0 ISR, the value in SFRPAGE register is overwritten with the contents of ...

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C8051F58x/F59x SFRNEXT popped to SFRPAGE Figure 13.6. SFR Page Stack Upon Return From CAN0 Interrupt In the example above, all three bytes in the SFR Page Stack are accessible via the SFRPAGE, SFRNEXT, and SFRLAST special function registers. If the ...

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SFR Definition 13.1. SFR0CN: SFR Page Control Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0x84; SFR Page = 0x0F Bit Name 7:1 Unused Read = 0000000b; Write = Don’t Care 0 SFRPGEN SFR Automatic ...

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C8051F58x/F59x SFR Definition 13.2. SFRPAGE: SFR Page Bit 7 6 Name Type 0 0 Reset SFR Address = 0xA7; SFR Page = All Pages Bit Name 7:0 SFRPAGE[7:0] SFR Page Bits. Represents the SFR Page the C8051 core uses when ...

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SFR Definition 13.3. SFRNEXT: SFR Next Bit 7 6 Name Type 0 0 Reset SFR Address = 0x85; SFR Page = All Pages Bit Name 7:0 SFRNEXT[7:0] SFR Page Bits. This is the value that will go to the SFR ...

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C8051F58x/F59x SFR Definition 13.4. SFRLAST: SFR Last Bit 7 6 Name Type 0 0 Reset SFR Address = 0xA7; SFR Page = All Pages Bit Name 7:0 SFRLAST[7:0] SFR Page Stack Bits. This is the value that will go to ...

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Table 13.1. Special Function Register (SFR) Memory Map for Pages 0x00, 0x10, and 0x0F 0(8) 1(9) 2( SPI0CN PCA0L PCA0H PCA1L PCA1H 10 SN0 SN1 P0MAT P0MASK (All Pages) 10 P0MDIN P1MDIN 0F E8 ...

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C8051F58x/F59x Table 13.1. Special Function Register (SFR) Memory Map for Pages 0x00, 0x10, and 0x0F TMR3CN TMR3RLL (All Pages) TMR5CN TMR5CAPL TCON TMOD TL0 (All Pages) (All Pages) (All Pages ...

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Table 13.2. Special Function Register (SFR) Memory Map for Page 0x0C 0(8) 1(9) 2(A) F8 CAN0IF2DA2L CAN0IF2DA2H CAN0IF2DB1L CAN0IF2DB1H CAN0IF2DB2L F0 B CAN0IF2A2L (All Pages) E8 CAN0IF2M1L CAN0IF2M1H CAN0IF2M2L CAN0IF2M2H E0 ACC CAN0IF2CML CAN0IF2CMH (All Pages) D8 CAN0IF1DB1L CAN0IF1DB1H CAN0IF1DB2L ...

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C8051F58x/F59x Table 13.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 ...

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Table 13.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address FLSCL 0xB6 Flash Scale IE 0xA8 Interrupt Enable IP 0xB8 Interrupt Priority IT01CF 0xE4 INT0/INT1 Configuration LIN0ADR 0xD3 LIN0 Address ...

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C8051F58x/F59x Table 13.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address P4MDOUT 0xAF Port 4 Output Mode Configuration PCA0CN 0xD8 PCA0 Control PCA0CPH0 0xFC PCA0 Capture 0 High PCA0CPH1 0xEA ...

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Table 13.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address PCA1CPL11 0xCE PCA1 Capture 11 Low PCA1CPM6 0xDA PCA1 Module 6 Mode Register PCA1CPM7 0xDB PCA1 Module 7 Mode Register ...

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C8051F58x/F59x Table 13.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address SN3 0xFC Serial Number 3 SP 0x81 Stack Pointer SPI0CFG 0xA1 SPI0 Configuration SPI0CKR 0xA2 SPI0 Clock Rate Control ...

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Table 13.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address XBR1 0xE2 Port I/O Crossbar Control 1 XBR2 0xC7 Port I/O Crossbar Control 2 XBR3 0xC6 Port I/O Crossbar Control ...

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C8051F58x/F59x 14. Interrupts The C8051F58x/F59x devices include an extended interrupt system supporting a total of 23 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and exter- nal inputs pins varies according to the specific ...

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Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior- ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be ...

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C8051F58x/F59x Table 14.1. Interrupt Summary Interrupt Source Interrupt Vector Reset 0x0000 External Interrupt 0 0x0003 (INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B ADC0 ...

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Table 14.1. Interrupt Summary Interrupt Source Interrupt Vector UART1 0x0093 Programmable Coun- 0x009B ter Array 1 Comparator2 0x00A3 Timer 4 Overflow 0x00AB Timer 5 Overflow 0x00B3 *Note: The LIN0INT bit is cleared by setting RSTINT (LINCTRL.3) 14.2. Interrupt Register Descriptions ...

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C8051F58x/F59x SFR Definition 14.1. IE: Interrupt Enable Bit ESPI0 Name R/W R/W Type 0 0 Reset SFR Address = 0xA8; Bit-Addressable; SFR Page = All Pages Bit Name 7 EA Enable All Interrupts. Globally enables/disables all interrupts. ...

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SFR Definition 14.2. IP: Interrupt Priority Bit 7 6 PSPI0 Name R R/W Type 1 0 Reset SFR Address = 0xB8; Bit-Addressable; SFR Page = All Pages Bit Name 7 Unused Read = 1b, Write = Don't Care. 6 PSPI0 ...

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C8051F58x/F59x SFR Definition 14.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 ELIN0 ET3 Name R/W R/W Type 0 0 Reset SFR Address = 0xE6; SFR Page = All Pages Bit Name 7 ELIN0 Enable LIN0 Interrupt. This bit sets ...

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SFR Definition 14.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 PLIN0 PT3 Name R/W R/W Type 0 0 Reset SFR Address = 0xF6; SFR Page = All Pages Bit Name 7 PLIN0 LIN0 Interrupt Priority Control. This bit sets ...

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C8051F58x/F59x SFR Definition 14.5. EIE2: Extended Interrupt Enable 2 Bit 7 6 ET5 ET4 Name R/W R/W Type 0 0 Reset SFR Address = 0xE7; SFR Page = All Pages Bit Name 7 ET5 Enable Timer 5 Interrupt. This bit ...

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SFR Definition 14.6. EIP2: Extended Interrupt Priority Enabled 2 Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Address = 0xF7; SFR Page = All Pages Bit Name 7 PT5 Timer 5 Interrupt Priority Control. This bit sets ...

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C8051F58x/F59x 14.3. External Interrupts INT0 and INT1 The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select ...

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SFR Definition 14.7. IT01CF: INT0/INT1 Configuration Bit 7 6 IN1PL IN1SL[2:0] Name R/W Type 0 0 Reset SFR Address = 0xE4; SFR Page = 0x0F Bit Name 7 IN1PL INT1 Polarity. 0: INT1 input is active low. 1: INT1 input ...

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... The simplest means of programming the Flash memory is through the C2 interface using programming tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initial- ized device. For details on the C2 commands to program Flash memory, see Section “30. C2 Interface” on page 349 ...

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Clear the PSWE and PSEE bits. 15.1.3. Flash Write Procedure Flash bytes are programmed by software with the following sequence: 1. Disable interrupts (recommended writing to an address in Banks set the COBANK[1:0] ...

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C8051F58x/F59x 15.2. Non-volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the ...

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The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing ...

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C8051F58x/F59x 15.4. Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified ...

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System Clock 1. If operating from an external crystal, be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. If the system is operating in an electrically noisy environment, ...

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C8051F58x/F59x SFR Definition 15.2. FLKEY: Flash Lock and Key Bit 7 6 Name Type 0 0 Reset SFR Address = 0xB7; SFR Page = All Pages Bit Name 7:0 FLKEY[7:0] Flash Lock and Key Register. Write: This register provides a ...

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SFR Definition 15.3. FLSCL: Flash Scale Bit 7 6 Name Reserved Reserved Reserved Type R/W R/W Reset 0 0 SFR Address = 0xB6; SFR Page = All Pages Bit Name 7:5 Reserved Must Write 000b. 4 FLRT Flash Read Time ...

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C8051F58x/F59x SFR Definition 15.4. CCH0CN: Cache Control Bit 7 6 Name Reserved Reserved CHPFEN Type R/W R/W Reset 0 0 SFR Address = 0xE3; SFR Page = 0x0F Bit Name 7:6 Reserved Must Write 00b 5 CHPFEN Cache Prefect Enable ...

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Power Management Modes The C8051F58x/F59x devices have three software programmable power management modes: Idle, Stop, and Suspend. Idle mode and Stop mode are part of the standard 8051 architecture, while Suspend mode is an enhanced power-saving mode implemented by ...

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C8051F58x/F59x 16.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital ...

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SFR Definition 16.1. PCON: Power Control Bit 7 6 Name Type 0 0 Reset SFR Address = 0x87; SFR Page = All Pages Bit Name 7:2 GF[5:0] General Purpose Flags 5–0. These are general purpose flags for use under software ...

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C8051F58x/F59x 17. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:  CIP-51 halts program execution  Special Function Registers (SFRs) are initialized to ...

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Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the V ...

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... A POR will force the VDD Monitor to the low threshold setting which is guaranteed to be below the un- calibrated output of the internal regulator. The device will then exit reset and resume normal operation for this reason Silicon Labs strongly recommends that the V (i.e. default value upon POR). ...

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SFR Definition 17.1. VDM0CN: V Bit 7 6 VDMEN VDDSTAT VDMLVL Name R/W R Type Varies Varies Reset SFR Address = 0xFF; SFR Page = 0x00 Bit Name 7 VDMEN V Monitor Enable. DD This bit turns the V tem ...

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C8051F58x/F59x 17.5. Comparator0 Reset Comparator0 can be configured as a reset source by writing the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on ...

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SFR Definition 17.2. RSTSRC: Reset Source Bit 7 6 Name FERROR C0RSEF Type R R Reset 0 Varies Varies SFR Address = 0xEF; SFR Page = 0x00 Bit Name Description 7 Unused Unused. 6 FERROR Flash Error Reset Flag. 5 ...

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C8051F58x/F59x 18. External Data Memory Interface and On-Chip XRAM For C8051F58x/F59x devices RAM are included on-chip and mapped into the external data mem- ory space (XRAM). Additionally, an External Memory Interface (EMIF) is available on the C8051F580/1/4/5 ...

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Configuring the External Memory Interface Configuring the External Memory Interface consists of five steps: 1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is most common), and skip the associated pins in ...

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C8051F58x/F59x Table 18.1. EMIF Pinout (C8051F580/1/4/5) Multiplexed Mode Signal Name Port Pin RD WR ALE D0/A0 D1/A1 D2/A2 D3/A3 D4/A4 D5/A5 D6/A6 D7/ A10 A11 A12 A13 A14 A15 — — — — — — — 158 Non ...

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Table 18.2. EMIF Pinout (C8051F588/9-F590/1) Multiplexed Mode Signal Name Port Pin RD P1.6 WR P1.7 ALE P1.5 D0/A0 P3.0 D1/A1 P3.1 D2/A2 P3.2 D3/A3 P3.3 D4/A4 P3.4 D5/A5 P3.5 D6/A6 P3.6 D7/A7 P3.7 A8 P2.0 A9 P2.1 A10 P2.2 A11 ...

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C8051F58x/F59x SFR Definition 18.1. EMI0CN: External Memory Interface Control Bit 7 6 Name Type Reset 0 0 SFR Address = 0xAA; SFR Page = 0x00 Bit Name 7:0 PGSEL[7:0] XRAM Page Select Bits. The XRAM Page Select Bits provide the ...

Page 161

SFR Definition 18.2. EMI0CF: External Memory Configuration Bit 7 6 Name Type Reset 0 0 SFR Address = 0xB2; SFR Page = 0x0F Bit Name 7:5 Unused Read = 000b; Write = Don’t Care. 4 EMD2 EMIF Multiplex Mode Select ...

Page 162

C8051F58x/F59x 18.4. Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 18.4.1. Multiplexed Configuration In Multiplexed mode, the Data Bus ...

Page 163

Non-multiplexed Configuration In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non- multiplexed Configuration is shown in Figure 18.2. See Section “18.6.1. Non-Multiplexed Mode” on page 167 for more information ...

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C8051F58x/F59x 18.5. Memory Mode Selection The external data memory space can be configured in one of four modes, shown in Figure 18.3, based on the EMIF Mode bits in the EMI0CF register (SFR Definition 18.2). These modes are summarized below. ...

Page 165

Split Mode with Bank Select When EMI0CF[3:2] are set to 10, the XRAM memory map is split into two areas, on-chip space and off- chip space.  Effective addresses below the internal XRAM size boundary will access on-chip XRAM ...

Page 166

C8051F58x/F59x SFR Definition 18.3. EMI0TC: External Memory Timing Control Bit 7 6 EAS[1:0] Name R/W Type 1 1 Reset SFR Address = 0xAA; SFR Page = 0x0F Bit Name 7:6 EAS[1:0] EMIF Address Setup Time Bits. 00: Address setup time ...

Page 167

Non-Multiplexed Mode 18.6.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111 ADDR[15:8] ADDR[7:0] DATA[7:0] /WR /RD ADDR[15:8] P2 ADDR[7:0] DATA[7:0] /RD /WR Figure 18.4. Non-multiplexed 16-bit MOVX Timing C8051F58x/F59x Nonmuxed 16-bit WRITE EMIF ADDRESS (8 MSBs) from DPH EMIF ...

Page 168

C8051F58x/F59x 18.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111 ADDR[15:8] ADDR[7:0] DATA[7:0] /WR /RD ADDR[15:8] ADDR[7:0] DATA[7:0] /RD /WR Figure 18.5. Non-multiplexed 8-bit MOVX without Bank Select Timing 168 Nonmuxed 8-bit WRITE without Bank Select EMIF ADDRESS ...

Page 169

MOVX with Bank Select: EMI0CF[4:2] = 110 ADDR[15:8] ADDR[7:0] DATA[7:0] /WR /RD ADDR[15:8] ADDR[7:0] DATA[7:0] /RD /WR Figure 18.6. Non-multiplexed 8-bit MOVX with Bank Select Timing C8051F58x/F59x Nonmuxed 8-bit WRITE with Bank Select EMIF ADDRESS (8 MSBs) from ...

Page 170

C8051F58x/F59x 18.6.2. Multiplexed Mode 18.6.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] T ALEH ALE /WR /RD ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] T ALEH ALE /RD /WR Figure 18.7. Multiplexed ...

Page 171

MOVX without Bank Select: EMI0CF[4:2] = 001 or 011 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE /WR /RD ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE /RD ...

Page 172

C8051F58x/F59x 18.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE /WR /RD ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE /RD /WR ...

Page 173

Table 18.3. AC Parameters for External Memory Interface Parameter Description T Address/Control Setup Time ACS T Address/Control Pulse Width ACW T Address/Control Hold Time ACH T Address Latch Enable High Time ALEH T Address Latch Enable Low Time ALEL T ...

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C8051F58x/F59x 19. Oscillators and Clock Selection C8051F58x/F59x devices include a programmable internal high-frequency oscillator, an external oscillator drive circuit, and a clock multiplier. The internal oscillator can be enabled/disabled and calibrated using the OSCICN, OSCICRS, and OSCIFIN registers, as shown ...

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SFR Definition 19.1. CLKSEL: Clock Select Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0x8F; SFR Page = 0x0F; Bit Name 7:2 Unused Read = 000000b; Write = Don’t Care 1:0 CLKSL[1:0] System Clock Source ...

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C8051F58x/F59x 19.2. Programmable Internal Oscillator All C8051F58x/F59x devices include a programmable internal high-frequency oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICRS and OSCIFIN registers defined in SFR ...

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SFR Definition 19.2. OSCICN: Internal Oscillator Control Bit 7 6 IOSCEN[1:0] SUSPEND Name R/W R/W Type 1 1 Reset SFR Address = 0xA1; SFR Page = 0x0F; Bit Name 7:6 IOSCEN[1:0] Internal Oscillator Enable Bits. 00: Oscillator Disabled. 01: Reserved. ...

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C8051F58x/F59x SFR Definition 19.3. OSCICRS: Internal Oscillator Coarse Calibration Bit 7 6 Name R Type 0 Varies Reset SFR Address = 0xA2; SFR Page = 0x0F; Bit Name 7 Unused Read = 0; Write = Don’t Care 6:0 OSCICRS[6:0] Internal ...

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Clock Multiplier The Clock Multiplier generates an output clock which is 4 times the input clock frequency scaled by a pro- grammable factor of 1, 2/3, 2/4 (or 1/2), 2/5, 2/6 (or 1/3), or 2/7. The Clock Multiplier’s input ...

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C8051F58x/F59x SFR Definition 19.5. CLKMUL: Clock Multiplier Bit 7 6 MULEN MULINIT MULRDY Name R/W R/W Type 0 0 Reset SFR Address = 0x97; SFR Page = 0x0F; Bit Name 7 MULEN Clock Multiplier Enable. 0: Clock Multiplier disabled. 1: ...

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External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator must ...

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C8051F58x/F59x SFR Definition 19.6. OSCXCN: External Oscillator Control Bit 7 6 XTLVLD XOSCMD[2:0] Name R Type 0 0 Reset SFR Address = 0x9F; SFR Page = 0x0F; Bit Name 7 XTLVLD Crystal Oscillator Valid Flag. (Read only when XOSCMD = ...

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External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 19.1, Option 1. The External Oscillator Frequency Control value (XFCN) should ...

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C8051F58x/F59x 32.768 kHz 22pF* * Capacitor values depend on crystal specifications Figure 19.3. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 19.4.2. External RC Example network is used as an external oscillator source for the MCU, the ...

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Equation 19.2. C Mode Oscillator Frequency For example: Assume V = 2.1 V and kHz VDD) 0.075 MHz = 2.1) Since the frequency of roughly 75 ...

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C8051F58x/F59x 20. Port Input/Output Digital and analog resources are available through 40 (C8051F580/1/4/5), 33 (C8051F588/9-F590/ (C8051F582/3/6/7) I/O pins. Port pins P0.0-P4.7 on the C8051F580/1/4/5, Port pins P0.0-P4.0 on the C8051F588/9-F590/1 and Port pins P0.0-P3.0 on the C8051F582/3/6/7 can ...

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Highest 2 UART0 Priority 2 CAN0 4 SPI0 2 SMBus0 4 CP0 2 CP1 /SYSCLK 7 PCA0 T0, T1, 4 /INT0, /INT1 2 LIN0 2 UART1 2 CP2 7 PCA1 2 T4 Lowest 2 T5 Priority ...

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C8051F58x/F59x 20.1. Port I/O Modes of Operation Port pins P0.0–P3.7 use the Port I/O cell shown in Figure 20.2. Each of these Port I/O cells can be config- ured by software for analog I/O or digital I/O using the PnMDIN ...

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Interfacing Port I Multi-Voltage System All Port I/O are capable of interfacing to digital logic operating at a supply voltage higher than VDD and less than 5.25 V. Connect the VIO pin to the voltage source of ...

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C8051F58x/F59x Table 20.2. Port I/O Assignment for Digital Functions Digital Function Any pin used for GPIO *Note: P3.1–P3.7 and P4.0 are only available on the 48-pin and 40-pin packages.  P4.1-P4.7 are only available on the 48-pin packages. A skip ...

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Important Note on Crossbar Configuration Port pin is claimed by a peripheral without use of the Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.0 if VREF is used, P0.1 if the ADC is configured ...

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C8051F58x/F59x UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART RX0 is always assigned to P0.5. CAN0 pin assignments are fixed to P0.6 for CAN_TX and P0.7 for CAN_RX. Standard Port I/Os appear ...

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... Crossbar is enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode Table alternative, the Configuration Wizard utility of the Silicon Labs IDE software will deter- mine the Port I/O pin-assignments based on the XBRn Register settings. ...

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C8051F58x/F59x SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0 Bit 7 6 CP1AE CP1E Name R/W R/W Type 0 0 Reset SFR Address = 0xE1; SFR Page = 0x0F Bit Name 7 CP1AE Comparator1 Asynchronous Output Enable. 0: Asynchronous ...

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SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1 Bit 7 6 T1E T0E Name R/W R/W Type 0 0 Reset SFR Address = 0xE2; SFR Page = 0x0F Bit Name 7 T1E T1 Enable unavailable at Port ...

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C8051F58x/F59x SFR Definition 20.3. XBR2: Port I/O Crossbar Register 2 Bit 7 6 Name WEAKPUD XBARE R/W R/W Type 0 0 Reset SFR Address = 0xC7; SFR Page = 0x0F Bit Name 7 WEAKPUD Port I/O Weak Pullup Disable. 0: ...

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SFR Definition 20.4. XBR3: Port I/O Crossbar Register 3 Bit 7 6 T5EXE T5E Name R/W R/W Type 0 0 Reset SFR Address = 0xC6; SFR Page = 0x0F Bit Name 7 T5EXE T5EX Enable. 0: T5EX unavailable at Port ...

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C8051F58x/F59x 20.5. Port Match Port match functionality allows system events to be triggered by a logic value change on P0, P1 P3. A software controlled value stored in the PnMATCH registers specifies the expected or normal logic values ...

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SFR Definition 20.7. P1MASK: Port 1 Mask Register Bit 7 6 Name Type 0 0 Reset SFR Address = 0xF4; SFR Page = 0x00 Bit Name 7:0 P1MASK[7:0] Port 1 Mask Value. Selects P1 pins to be compared to the ...

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C8051F58x/F59x SFR Definition 20.9. P2MASK: Port 2 Mask Register Bit 7 6 Name Type 0 0 Reset SFR Address = 0xB2; SFR Page = 0x00 Bit Name 7:0 P2MASK[7:0] Port 2 Mask Value. Selects P2 pins to be compared to ...

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