C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 196

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C8051F581-IMR

Manufacturer Part Number
C8051F581-IMR
Description
8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F581-IMR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
C8051F58x/F59x
SFR Definition 20.3. XBR2: Port I/O Crossbar Register 2
SFR Address = 0xC7; SFR Page = 0x0F
196
Name WEAKPUD
Reset
5:4
Bit
Type
7
6
3
2
1
0
Bit
WEAKPUD
Reserved
XBARE
CP2AE
URT1E
LIN0E
Name
CP2E
R/W
7
0
Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog
mode).
1: Weak Pullups disabled.
Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
Always Write to 00b.
Comparator2 Asynchronous Output Enable.
0: Asynchronous CP2 unavailable at Port pin.
1: Asynchronous CP2 routed to Port pin.
Comparator2 Output Enable.
0: CP2 unavailable at Port pin.
1: CP2 routed to Port pin.
UART1 I/O Output Enable.
0: UART1 I/O unavailable at Port pin.
1: UART1 TX0, RX0 routed to Port pins.
LIN I/O Output Enable.
0: LIN I/O unavailable at Port pin.
1: LIN_TX, LIN_RX routed to Port pins.
XBARE
R/W
6
0
R/W
5
0
Reserved
Rev. 1.2
R/W
4
0
Function
CP2AE
R/W
3
0
CP2E
R/W
2
0
URT1E
R/W
1
0
LIN0E
R/W
0
0

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