C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 10

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F58x/F59x
10
Figure 13.4. SFR Page Stack Upon PCA Interrupt Occurring During a CAN0 ISR 110
Figure 13.5. SFR Page Stack Upon Return From PCA Interrupt .......................... 111
Figure 13.6. SFR Page Stack Upon Return From CAN0 Interrupt ........................ 112
Figure 15.1. Flash Program Memory Map ............................................................. 140
Figure 17.1. Reset Sources ................................................................................... 150
Figure 17.2. Power-On and VDD Monitor Reset Timing ....................................... 151
Figure 19.1. Oscillator Options .............................................................................. 174
Figure 19.2. Example Clock Multiplier Output ....................................................... 179
Figure 19.3. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 184
Figure 20.1. Port I/O Functional Block Diagram .................................................... 187
Figure 20.2. Port I/O Cell Block Diagram .............................................................. 188
Figure 20.3. Peripheral Availability on Port I/O Pins .............................................. 191
Figure 20.4. Crossbar Priority Decoder in Example Configuration ........................ 192
Figure 21.1. LIN Block Diagram ............................................................................ 212
Figure 22.1. Typical CAN Bus Configuration ......................................................... 229
Figure 22.2. CAN Controller Diagram .................................................................... 230
Figure 22.3. Four segments of a CAN Bit .............................................................. 232
Figure 23.1. SMBus Block Diagram ...................................................................... 237
Figure 23.2. Typical SMBus Configuration ............................................................ 238
Figure 23.3. SMBus Transaction ........................................................................... 239
Figure 23.4. Typical SMBus SCL Generation ........................................................ 241
Figure 23.5. Typical Master Write Sequence ........................................................ 248
Figure 23.6. Typical Master Read Sequence ........................................................ 249
Figure 23.7. Typical Slave Write Sequence .......................................................... 250
Figure 23.8. Typical Slave Read Sequence .......................................................... 251
Figure 24.1. UART0 Block Diagram ...................................................................... 254
Figure 24.2. UART0 Timing Without Parity or Extra Bit ......................................... 256
Figure 24.3. UART0 Timing With Parity ................................................................ 256
Figure 24.4. UART0 Timing With Extra Bit ............................................................ 256
Figure 24.5. Typical UART Interconnect Diagram ................................................. 257
Figure 24.6. UART Multi-Processor Mode Interconnect Diagram ......................... 258
Figure 26.1. SPI Block Diagram ............................................................................ 270
Figure 26.2. Multiple-Master Mode Connection Diagram ...................................... 273
Figure 26.3. 3-Wire Single Master and 3-Wire Single Slave Mode 
Figure 26.4. 4-Wire Single Master Mode and 4-Wire Slave Mode 
Figure 26.5. Master Mode Data/Clock Timing ....................................................... 275
Figure 26.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 276
Figure 26.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 276
Figure 26.8. SPI Master Timing (CKPHA = 0) ....................................................... 280
Figure 26.9. SPI Master Timing (CKPHA = 1) ....................................................... 280
Figure 26.10. SPI Slave Timing (CKPHA = 0) ....................................................... 281
Figure 26.11. SPI Slave Timing (CKPHA = 1) ....................................................... 281
Figure 27.1. T0 Mode 0 Block Diagram ................................................................. 286
Connection Diagram .......................................................................... 273
Connection Diagram ......................................................................... 273
Rev. 1.2