C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 337
C8051F581-IMR
Manufacturer Part Number
C8051F581-IMR
Description
8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
Manufacturer
Silicon Labs
Datasheet
1.C8051F585-IQR.pdf
(356 pages)
Specifications of C8051F581-IMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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29.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA1 Counter and the module's 16-bit capture/compare register (PCA1CPHn and
PCA1CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA1CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not auto-
matically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared
by software. Setting the TOG1n, MAT1n, and ECOM1n bits in the PCA1CPMn register enables the High-
Speed Output mode. If ECOM1n is cleared, the associated pin will retain its state, and not toggle on the
next match event.
Important Note About Capture/Compare Registers : When writing a 16-bit value to the PCA1 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA1CPLn clears the
ECOM1n bit to 0; writing to PCA1CPHn sets ECOM1n to 1.
PCA1CPLn
Write to
Reset
PCA1CPHn
Write to
0
ENB
ENB
1
PCA1
Timebase
Figure 29.6. PCA1 High-Speed Output Mode Diagram
Enable
W
M
P
1
6
1
n
x
PCA1CPMn
C
O
M
E
1
n
PCA1CPLn
C
A
P
P
1
n
0 0
PCA1L
C
A
P
N
1
n
16-bit Comparator
M
A
T
n
1
O
G
T
1
n
W
P
M
1
n
0 x
E
C
C
F
1
n
PCA1CPHn
PCA1H
Rev. 1.2
Match
Toggle
C
F
1
TOG1n
C8051F58x/F59x
C
R
1
0
1
PCA1CN
C
C
F
1
1
C
C
F
1
0
0
1
C
C
F
9
CEXn
C
C
F
8
C
C
F
7
PCA1 Interrupt
C
C
F
6
Crossbar
Port I/O
337
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