C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 324

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F58x/F59x
The PCA0 clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL5 defaults to 0x00. Using Equation 28.5, this results in a WDT
timeout interval of 256 PCA0 clock cycles, or 3072 system clock cycles. Table 28.3 lists some example
timeout intervals for typical system clocks.
324
Notes:
System Clock (Hz)
1. Assumes SYSCLK/12 as the PCA0 clock source, and a PCA0L
2. Internal SYSCLK reset frequency = Internal Oscillator divided by
24,000,000
24,000,000
24,000,000
Table 28.3. Watchdog Timer Timeout Intervals
3,000,000
3,000,000
3,000,000
value of 0x00 at the update time.
128.
187,500
187,500
187,500
2
2
2
PCA0CPL5
Rev. 1.2
255
128
255
128
255
128
32
32
32
Timeout Interval (ms)
262.1
132.1
4194
2114
32.8
16.5
33.8
541
4.2
1