C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 343

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

29.4. Register Descriptions for PCA1
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Definition 29.1. PCA1CN: PCA1 Control
SFR Address = 0xD8; Bit-Addressable; SFR Page = 0x10
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
CCF10
CCF11
Name
CCF9
CCF8
CCF7
CCF6
CR1
CF1
CF1
R/W
7
0
PCA1 Counter/Timer Overflow Flag.
Set by hardware when the PCA1 Counter/Timer overflows from 0xFFFF to 0x0000.
When the Counter/Timer Overflow (CF1) interrupt is enabled, setting this bit causes the
CPU to vector to the PCA1 interrupt service routine. This bit is not automatically
cleared by hardware and must be cleared by software.
PCA1 Counter/Timer Run Control.
This bit enables/disables the PCA1 Counter/Timer.
0: PCA1 Counter/Timer disabled.
1: PCA1 Counter/Timer enabled.
PCA1 Module 11 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF11 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA1 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
PCA1 Module 10 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF10 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA1 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
PCA1 Module 9 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF9 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA1 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
PCA1 Module 8 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF8 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA1 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
PCA1 Module 7 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF7 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA1 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
PCA1 Module 6 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF6 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA1 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
CR1
R/W
6
0
CCF6
R/W
5
0
CCF7
R/W
Rev. 1.2
4
0
Function
CCF8
R/W
3
0
C8051F58x/F59x
CCF9
R/W
2
0
CCF10
R/W
1
0
CCF11
R/W
0
0
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