C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 322

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F58x/F59x
28.4. Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA0 Module 5. The WDT is
used to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a
specified limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 5 operates as a watchdog timer (WDT). The Mod-
ule 2 high byte is compared to the PCA0 counter high byte; the Module 2 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA0 registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset
shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and option-
ally re-configured and re-enabled if it is used in the system).
28.4.1. Watchdog Timer Operation
While the WDT is enabled:






While the WDT is enabled, writes to the CR bit will not change the PCA0 counter state; the counter will run
until the WDT is disabled. The PCA0 counter run control bit (CR) will read zero if the WDT is enabled but
user software has not enabled the PCA0 counter. If a match occurs between PCA0CPH5 and PCA0H
while the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated
with a write of any value to PCA0CPH5. Upon a PCA0CPH5 write, PCA0H plus the offset held in
PCA0CPL5 is loaded into PCA0CPH5 (See Figure 28.11).
322
PCA0CPLn
PCA0 counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA0 clock source bits (CPS2 – CPS0) are frozen.
PCA0 Idle control bit (CIDL) is frozen.
PCA0 Module 5 is forced into software timer mode.
Writes to the Module 5 mode register (PCA0CPM5) are disabled.
Write to
Reset
PCA0CPHn
Write to
0
ENB
ENB
1
W
P
M
1
6
n
1
O
M
E
C
n
PCA0CPMn
C
A
P
P
n
0 0 x 0
C
A
P
N
n
M
A
T
n
PCA0 Timebase
O
G
T
n
W
P
M
n
E
C
C
F
n
x
Figure 28.10. PCA0 16-Bit PWM Mode
Enable
PCA0CPHn
PCA0H
16-bit Comparator
Rev. 1.2
PCA0CPLn
PCA0L
Overflow
match
S
R
SET
CLR
Q
Q
CEXn
Crossbar
Port I/O