C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 6

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F58x/F59x
22. Controller Area Network (CAN0) ........................................................................ 229
23. SMBus................................................................................................................... 237
24. UART0 ................................................................................................................... 254
25. UART1 ................................................................................................................... 263
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21.4. LIN Slave Mode Operation ............................................................................ 217
21.5. Sleep Mode and Wake-Up ............................................................................ 218
21.6. Error Detection and Handling ........................................................................ 218
21.7. LIN Registers................................................................................................. 219
22.1. Bosch CAN Controller Operation................................................................... 230
22.2. CAN Registers............................................................................................... 233
23.1. Supporting Documents .................................................................................. 238
23.2. SMBus Configuration..................................................................................... 238
23.3. SMBus Operation .......................................................................................... 238
23.4. Using the SMBus........................................................................................... 240
23.5. SMBus Transfer Modes................................................................................. 247
23.6. SMBus Status Decoding................................................................................ 251
24.1. Baud Rate Generator .................................................................................... 254
24.2. Data Format................................................................................................... 256
24.3. Configuration and Operation ......................................................................... 257
25.1. Enhanced Baud Rate Generation.................................................................. 264
25.2. Operational Modes ........................................................................................ 265
21.7.1. LIN Direct Access SFR Registers Definitions ....................................... 219
21.7.2. LIN Indirect Access SFR Registers Definitions ..................................... 221
22.1.1. CAN Controller Timing .......................................................................... 230
22.1.2. CAN Register Access............................................................................ 231
22.1.3. Example Timing Calculation for 1 Mbit/Sec Communication ................ 231
22.2.1. CAN Controller Protocol Registers........................................................ 233
22.2.2. Message Object Interface Registers ..................................................... 233
22.2.3. Message Handler Registers.................................................................. 233
22.2.4. CAN Register Assignment .................................................................... 234
23.3.1. Transmitter Vs. Receiver....................................................................... 239
23.3.2. Arbitration.............................................................................................. 239
23.3.3. Clock Low Extension............................................................................. 239
23.3.4. SCL Low Timeout.................................................................................. 239
23.3.5. SCL High (SMBus Free) Timeout ......................................................... 240
23.4.1. SMBus Configuration Register.............................................................. 240
23.4.2. SMB0CN Control Register .................................................................... 244
23.4.3. Data Register ........................................................................................ 247
23.5.1. Write Sequence (Master) ...................................................................... 248
23.5.2. Read Sequence (Master) ...................................................................... 249
23.5.3. Write Sequence (Slave) ........................................................................ 250
23.5.4. Read Sequence (Slave) ........................................................................ 251
24.3.1. Data Transmission ................................................................................ 257
24.3.2. Data Reception ..................................................................................... 257
24.3.3. Multiprocessor Communications ........................................................... 258
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