C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 190

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F58x/F59x
20.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions
External digital event capture functions can be used to trigger an interrupt or wake the device from a low
power mode when a transition occurs on a digital I/O pin. The digital event capture functions do not require
dedicated pins and will function on both GPIO pins (PnSKIP = 1) and pins in use by the Crossbar (PnSKIP
= 0). External digital event capture functions cannot be used on pins configured for analog I/O. Table 20.3
shows all available external digital event capture functions.
20.3. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 20.3) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource excluding UART0, which is always assigned to pins P0.4 and P0.5, and excluding CAN0 which is
always assigned to pins P0.6 and P0.7. If a Port pin is assigned, the Crossbar skips that pin when assign-
ing the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in the
PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that are to be used for
analog input, dedicated functions, or GPIO.
Because of the nature of Priority Crossbar Decoder, not all peripherals can be located on all port pins.
Figure 20.3 maps peripherals to the potential port pins on which the peripheral I/O can appear.
190
Digital Function
Any pin used for GPIO
*Note: P3.1–P3.7 and P4.0 are only available on the 48-pin and 40-pin packages. 
Digital Function
External Interrupt 0
External Interrupt 1
Port Match
*Note: P3.1–P3.7 are only available on the 48-pin and 40-pin packages.
P4.1-P4.7 are only available on the 48-pin packages. A skip register is not available for P4.
Table 20.3. Port I/O Assignment for External Digital Event Capture Functions
Table 20.2. Port I/O Assignment for Digital Functions
Potentially Assignable Port Pins
Potentially Assignable Port Pins
Rev. 1.2
P0.0–P4.7*
P0.0–P3.7*
P1.0–P1.7
P1.0–P1.7
P0MASK, P0MAT
P1MASK, P1MAT
P2MASK, P2MAT
P3MASK, P3MAT
P0SKIP, P1SKIP,
SFR(s) used for
P2SKIP, P3SKIP
SFR(s) used for
Assignment
Assignment
IT01CF
IT01CF