C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 305

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F58x/F59x
27.4. Timer 4 and Timer 5
Timers 4 and 5 are 16-bit counter/timers, each formed by two 8-bit SFRs: TMRnL (low byte) and TMRnH
(high byte) where n = 4 and 5 for timers 4 and 5 respectively. Timers 4 and 5 feature auto-reload, capture,
and toggle output modes with the ability to count up or down. Capture mode and Auto-Reload mode are
selected using bits in the Timer4 and 5 Control registers (TMRnCN). Toggle Output mode is selected using
the Timer 4 and 5 Configuration registers (TMRnCF). These timers may also be used to generate a
square-wave at an external pin. As with Timers 0 and 1, Timers 4 and 5 can use either the system clock
(divided by one, two, or twelve), external clock (divided by eight) or transitions on an external input pin as
its clock source.
The Counter/Timer Select bit CTn bit (TMRnCN.1) configures the peripheral as a counter or timer. Clearing
CTn to 0 configures the Timer to be in a timer mode (i.e., the system clock or transitions on an external pin
as the input for the timer). When CTn is set to 1, the timer is configured as a counter (i.e., high-to-low tran-
sitions at the Tn input pin increment (or decrement) the counter/timer register. Refer to Section “
20.4. Port
I/O Initialization
” on page
193
for information on selecting and configuring external I/O pins for digital
peripherals, such as the Tn pin.
The Timers can use either SYSCLK, SYSCLK divided by 2, SYSCLK divided by 12, an external clock
divided by 8, or high-to-low transitions on the Tn input pin as its clock source when operating in Coun-
ter/Timer with Capture mode. Clearing the CTn bit (TMRnCN.1) selects the system clock/external clock as
the input for the timer. The Timer Clock Select bits TnM0 and TnM1 in TMRnCF can be used to select the
system clock undivided, system clock divided by two, system clock divided by 12, or an external clock pro-
vided at the XTAL1/XTAL2 pins divided by 8 (see SFR Definition 27.19). When CTn is set to logic 1, a high-
to-low transition at the Tn input pin increments the counter/timer register (i.e., configured as a counter).
27.4.1. Configuring Timer 4 and 5 to Count Down
Timers 4 and 5 have the ability to count down. When the timer’s Decrement Enable Bit (DCENn) in the
Timer Configuration Register (see SFR Definition 27.19) is set to 1, the timer can then count up or down .
When DCENn = 1, the direction of the timer’s count is controlled by the TnEX pin’s logic level. When
TnEX = 1, the counter/timer will count up; when TnEX = 0, the counter/timer will count down. To use this
feature, TnEX must be enabled in the digital crossbar and configured as a digital input.
Note: When DCENn = 1, other functions of the TnEX input (i.e., capture and auto-reload) are not available. TnEX will
only control the direction of the timer when DCENn = 1.
27.4.2. Capture Mode
In Capture Mode, Timers 4 and 5 will operate as a 16-bit counter/timer with capture facility. When the Timer
External Enable bit (see SFR Definition 27.18) is set to 1, a high-to-low transition on the TnEX input pin
causes the 16-bit value in the associated timer (THn, TLn) to be loaded into the capture registers (TMRn-
CAPH, TMRnCAPL). If a capture is triggered in the counter/timer, the Timer External Flag (TMRnCN.6) will
be set to 1 and an interrupt will occur if the interrupt is enabled. See
Section “14. Interrupts” on
page 126
for further information concerning the configuration of interrupt sources.
As the 16-bit timer register increments and overflows TMRnH:TMRnL, the TFn Timer Overflow/Underflow
Flag (TMRnCN.7) is set to 1 and an interrupt will occur if the interrupt is enabled. The timer can be config-
ured to count down by setting the Decrement Enable Bit (TMRnCF.0) to 1. This will cause the timer to dec-
rement with every timer clock/count event and underflow when the timer transitions from 0x0000 to
0xFFFF. Just as in overflows, the Overflow/Underflow Flag (TFn) will be set to 1, and an interrupt will occur
if enabled.
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