C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 314

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F58x/F59x
28.2. PCA0 Interrupt Sources
Figure 28.3 shows a diagram of the PCA0 interrupt tree. There are five independent event flags that can
be used to generate a PCA0 interrupt. They are as follows: the main PCA0 counter overflow flag (CF),
which is set upon a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF), which can
be set on an overflow from the 8th, 9th, 10th, or 11th bit of the PCA0 counter, and the individual flags for
each PCA0 channel (CCF0, CCF1, CCF2, CCF3, CCF4 and CCF5), which are set according to the opera-
tion mode of that module. These event flags are always set when the trigger condition occurs. Each of
these flags can be individually selected to generate a PCA0 interrupt, using the corresponding interrupt
enable flag (ECF for CF, ECOV for COVF, and ECCFn for each CCFn). PCA0 interrupts must be globally
enabled before any individual interrupt sources are recognized by the processor. PCA0 interrupts are glob-
ally enabled by setting the EA bit and the EPCA0 bit to logic 1.
314
PCA0 Counter/Timer 16-
PCA0 Counter/Timer 8,
9, 10 or 11-bit Overflow
bit Overflow
W
P
M
1
6
n
PCA Module 0
PCA Module 1
PCA Module 2
PCA Module 3
PCA Module 4
PCA Module 5
(for n = 0 to 2)
PCA0CPMn
E
C
O
M
n
C
A
P
P
(CCF0)
(CCF1)
(CCF2)
(CCF3)
(CCF4)
(CCF5)
n
C
A
P
N
n
M
A
T
n
O
G
T
n
W
M
P
n
E
C
C
F
n
C
F
C
R
PCA0CN
Figure 28.3. PCA0 Interrupt Block Diagram
C
C
F
5
C
C
F
4
C
C
F
3
C
C
F
2
C
C
F
1
C
C
F
0
ECCF0
ECCF1
ECCF2
ECCF3
ECCF4
ECCF5
C
D
L
I
W
D
E
T
PCA0MD
W
D
C
K
L
C
P
S
2
C
P
S
1
0
1
0
1
0
1
0
1
0
1
0
1
C
P
S
0
E
C
F
Rev. 1.2
0
1
A
R
S
E
L
PCA0PWM
C
O
V
F
O
E
C
V
0
1
C
L
S
E
L
1
C
L
S
E
L
0
Set 8, 9, 10, or 11 bit Operation
EPCA0
0
1
EA
0
1
Interrupt
Priority
Decoder