C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 310

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C8051F581-IMR

Manufacturer Part Number
C8051F581-IMR
Description
8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F581-IMR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
C8051F58x/F59x
SFR Definition 27.20. TMRnCAPL: Timer 4 and 5 Capture Register Low Byte
TMR4CAPL SFR Address = 0xCA; TMR5CAPL SFR Address = 0x92; SFR Page = 0x10
SFR Definition 27.21. TMRnCAPH: Timer 4 and 5 Capture Register High Byte
TMR4CAPH SFR Address = 0xCB; TMR5CAPH SFR Address = 0x93; SFR Page = 0x10
310
Name
Reset
Name
Reset
7:0 TMRnCAPL[7:0] Timer n Reload Register Low Byte.
7:0 TMRnCAPH[7:0] Timer n Reload Register High Byte.
Bit
Bit
Type
Type
Bit
Bit
Name
Name
7
0
7
0
TMRnCAPL captures the low byte of Timer 4 and 5 when Timer 4 and 5 are con-
figured in capture mode. When Timer 4 and 5 are configured in auto-reload
mode, it holds the low byte of the reload value.
TMRnCAPH captures the high byte of Timer 4 and 5 when Timer 4 and 5 are
configured in capture mode. When Timer 4 and 5 are configured in auto-reload
mode, it holds the high byte of the reload value.
6
0
6
0
5
0
5
0
Rev. 1.2
TMRnRLH[7:0]
TMRnRLL[7:0]
4
0
4
0
R/W
R/W
Function
Function
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0

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