C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 57

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

6.1.4. Burst Mode
Burst Mode is a power saving feature that allows ADC0 to remain in a very low power state between con-
versions. When Burst Mode is enabled, ADC0 wakes from a very low power state, accumulates 1, 4, 8, or
16 samples using an internal Burst Mode clock (approximately 25 MHz), then re-enters a very low power
state. Since the Burst Mode clock is independent of the system clock, ADC0 can perform multiple conver-
sions then enter a very low power state within a single system clock cycle, even if the system clock is slow
(e.g., 32.768 kHz), or suspended.
Burst Mode is enabled by setting BURSTEN to logic 1. When in Burst Mode, AD0EN controls the ADC0
idle power state (i.e. the state ADC0 enters when not tracking or performing conversions). If AD0EN is set
to logic 0, ADC0 is powered down after each burst. If AD0EN is set to logic 1, ADC0 remains enabled after
each burst. On each convert start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered
down, it will automatically power up and wait the programmable Power-Up Time controlled by the
AD0PWR bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 6.4 shows an exam-
ple of Burst Mode Operation with a slow system clock and a repeat count of 4.
Important Note: When Burst Mode is enabled, only Post-Tracking and Dual-Tracking modes can be used.
When Burst Mode is enabled, a single convert start will initiate a number of conversions equal to the repeat
count. When Burst Mode is disabled, a convert start is required to initiate each conversion. In both modes,
the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after “repeat count” conversions have
Convert Start
AD0INT Flag
AD0INT Flag
ADC0 State
ADC0 State
Time
Time
Figure 6.3. 12-Bit ADC Tracking Mode Example
F
F
Key
F
Sn
S1
S1
Track
Post-Tracking or Dual-Tracking Modes (AD0TK = ‘00')
Equal to one period of FCLK.
Each Sn is equal to one period of the SAR clock.
S2
S2
Convert
F
...
F
Rev. 1.2
S12
S1
Pre-Tracking Mode
S13
S2
Convert
F
...
C8051F58x/F59x
S12
S13
F
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