C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 341

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

29.3.5.2. 9/10/11-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be varied by writing to an “Auto-
Reload” Register, which is dual-mapped into the PCA1CPHn and PCA1CPLn register locations. The data
written to define the duty cycle should be right-justified in the registers. The auto-reload registers are
accessed (read or written) when the bit ARSEL1 in PCA1PWM is set to 1. The capture/compare registers
are accessed when ARSEL1 is set to 0.
When the least-significant N bits of the PCA1 counter match the value in the associated module’s cap-
ture/compare register (PCA1CPn), the output on CEXn is asserted high. When the counter overflows from
the Nth bit, CEXn is asserted low (see Figure 29.9). Upon an overflow from the Nth bit, the COVF1 flag is
set, and the value stored in the module’s auto-reload register is loaded into the capture/compare register.
The value of N is determined by the CLSEL1 bits in register PCA1PWM.
The 9, 10 or 11-bit PWM mode is selected by setting the ECOM1n and PWM1n bits in the PCA1CPMn reg-
ister, and setting the CLSEL1 bits in register PCA1PWM to the desired cycle length (other than 8-bits). If
the MAT1n bit is set to 1, the CCFn flag for the module will be set each time a comparator match (rising
edge) occurs. The COVF1 flag in PCA1PWM can be used to detect the overflow (falling edge), which will
occur every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) PCA1 clock cycles. The duty cycle for 9/10/11-Bit
PWM Mode is given in Equation 29.2, where N is the number of bits in the PWM cycle.
Important Note About PCA1CPHn and PCA1CPLn Registers : When writing a 16-bit value to the
PCA1CPn registers, the low byte should always be written first. Writing to PCA1CPLn clears the ECOM1n
bit to 0; writing to PCA1CPHn sets ECOM1n to 1.
A 0% duty cycle may be generated by clearing the ECOM1n bit to 0.
PCA1CPLn
Write to
Reset
PCA1CPHn
Write to
0
ENB
ENB
1
Figure 29.9. PCA1 9, 10 and 11-Bit PWM Mode Diagram
W
M
P
0
1
6
1
n
Equation 29.3. 9, 10, and 11-Bit PWM Duty Cycle
E
C
O
M
1
n
PCA1CPMn
C
A
P
P
1
n
0 0 x 0
C
A
P
N
1
n
M
A
T
n
1
O
G
T
1
n
W
M
P
1
n
E
C
C
F
1
n
x
PCA1 Timebase
Duty Cycle
ARSEL1 = 1
ARSEL1 = 0
R/W when
R/W when
Enable
N-bit Comparator
(Capture/Compare)
PCA1CPH:Ln
PCA1CPH:Ln
=
(Auto-Reload)
(right-justified)
(right-justified)
Rev. 1.2
PCA1H:L

----------------------------------------------- -
2 N PCA
–
2 N
Overflow of N
1
CPn
match

th
R
A
S
E
L
1
Bit
C8051F58x/F59x
O
S
R
PCA1PWM
C
V
F
1
C
O
E
V
1
x
CLR
SET
Q
Q
C
S
E
L
L
1
1
CEXn
C
L
S
E
L
1
0
Set “N” bits:
01 = 9 bits
10 = 10 bits
11 = 11 bits
Crossbar
Port I/O
341