C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 92

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F58x/F59x
With the CIP-51's maximum system clock at 50 MHz, it has a peak throughput of 50 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2).
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and mem-
ory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in “C2 Interface” on page 349.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's
debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-sys-
tem device programming and debugging. Third party macro assemblers and C compilers are also avail-
able.
92
Clocks to Execute
Number of Instructions
RESET
CLOCK
STOP
IDLE
1
26
ACCUMULATOR
Figure 11.1. CIP-51 Block Diagram
PROGRAM COUNTER (PC)
CONTROL
PSW
PRGM. ADDRESS REG.
LOGIC
PC INCREMENTER
POWER CONTROL
DATA POINTER
REGISTER
2
50
BUFFER
TMP1
PIPELINE
ALU
2/3
5
TMP2
Rev. 1.2
DATA BUS
DATA BUS
D8
D8
D8
3
14
A16
D8
D8
D8
D8
B REGISTER
REGISTER
INTERFACE
INTERFACE
INTERRUPT
INTERFACE
ADDRESS
MEMORY
SRAM
SFR
BUS
3/4
7
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
SFR_READ_DATA
SRAM
MEM_CONTROL
EMULATION_IRQ
MEM_ADDRESS
SFR_CONTROL
SFR_ADDRESS
SYSTEM_IRQs
4
3
4/5
1
5
2
8
1