C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 344

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F58x/F59x
SFR Definition 29.2. PCA1MD: PCA1 Mode
SFR Address = 0xD9; SFR Page = 0x10
344
Name
Reset
6:4
3:1 CPS1[2:0] PCA1 Counter/Timer Pulse Select.
Bit
Type
7
0
Bit
Unused
CIDL1
Name
EC1F
CIDL1
R/W
7
0
PCA1 Counter/Timer Idle Control.
Specifies PCA1 behavior when CPU is in Idle Mode.
0: PCA1 continues to function normally while the system controller is in Idle Mode.
1: PCA1 operation is suspended while the system controller is in Idle Mode.
Read = 000b, Write = Don't care.
These bits select the timebase source for the PCA1 counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
110: Timer 4 overflow
111: Timer 5 overflow
PCA1 Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA1 Counter/Timer Overflow (CF1) interrupt.
0: Disable the CF1 interrupt.
1: Enable a PCA1 Counter/Timer Overflow interrupt request when CF1 (PCA1CN.7) is
set.
R
6
0
R/W
5
0
Rev. 1.2
R
4
0
Function
CPS12
R/W
3
0
CPS11
R/W
2
0
CPS10
R/W
1
0
ECF1
R/W
0
0