C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 320

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F58x/F59x
28.3.5.2. 9/10/11-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be varied by writing to an “Auto-
Reload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The data
written to define the duty cycle should be right-justified in the registers. The auto-reload registers are
accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/compare registers
are accessed when ARSEL is set to 0.
When the least-significant N bits of the PCA0 counter match the value in the associated module’s cap-
ture/compare register (PCA0CPn), the output on CEXn is asserted high. When the counter overflows from
the Nth bit, CEXn is asserted low (see Figure 28.9). Upon an overflow from the Nth bit, the COVF flag is
set, and the value stored in the module’s auto-reload register is loaded into the capture/compare register.
The value of N is determined by the CLSEL bits in register PCA0PWM.
The 9, 10 or 11-bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn regis-
ter, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other than 8-bits). If the
MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator match (rising edge)
occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will occur
every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) PCA0 clock cycles. The duty cycle for 9/10/11-Bit PWM
Mode is given in Equation 28.2, where N is the number of bits in the PWM cycle.
Important Note About PCA0CPHn and PCA0CPLn Registers : When writing a 16-bit value to the
PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
320
PCA0CPLn
Write to
Reset
PCA0CPHn
R
A
S
E
L
0
Write to
C
O
PCA0PWM
E
V
C
O
V
F
x
0
ENB
ENB
1
C
L
S
E
L
1
0
C
L
S
E
L
0
0
W
M
P
1
6
n
0
Equation 28.3. 9, 10, and 11-Bit PWM Duty Cycle
E
C
O
M
n
PCA0CPMn
C
A
P
P
n
Figure 28.8. PCA0 8-Bit PWM Mode Diagram
0 0 x 0
C
A
P
N
n
M
A
T
n
O
G
T
n
W
M
P
n
C
C
E
F
n
x
PCA0 Timebase
Duty Cycle
Enable
=
PCA0CPHn
Comparator
PCA0CPLn
Rev. 1.2
PCA0L

----------------------------------------------- -
8-bit
2 N PCA0CPn
–
2 N
Overflow
COVF
match

S
R
SET
CLR
Q
Q
CEXn
Crossbar
Port I/O