C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 315

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

28.3. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: Edge-triggered
Capture, Software Timer, High Speed Output, Frequency Output, 8 to 11-Bit Pulse Width Modulator, or 16-
Bit Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the
CIP-51 system controller. These registers are used to exchange data with a module and configure the
module's mode of operation. Table 28.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM
registers used to select the PCA0 capture/compare module’s operating mode. All modules set to use 8, 9,
10, or 11-bit PWM mode must use the same cycle length (8-11 bits). Setting the ECCFn bit in a
PCA0CPMn register enables the module's CCFn interrupt.
28.3.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes PCA0 to capture the value of the PCA0 coun-
ter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the
state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or fall-
ing-edge caused the capture.
Bit Number
Capture triggered by positive edge on CEXn
Capture triggered by negative edge on CEXn
Capture triggered by any transition on CEXn
Software Timer
High Speed Output
Frequency Output
8-Bit Pulse Width Modulator (Note 7)
9-Bit Pulse Width Modulator (Note 7)
10-Bit Pulse Width Modulator (Note 7)
11-Bit Pulse Width Modulator (Note 7)
16-Bit Pulse Width Modulator
Notes:
1. X = Don’t Care (no functional difference for individual module if 1 or 0).
2. A = Enable interrupts for this module (PCA0 interrupt triggered on CCFn set to 1).
3. B = Enable 8th, 9th, 10th or 11th bit overflow interrupt (Depends on setting of CLSEL[1:0]).
4. C = When set to 0, the digital comparator is off. For high speed and frequency output modes, the
5. D = Selects whether the Capture/Compare register (0) or the Auto-Reload register (1) for the associated
6. E = When set, a match event will cause the CCFn flag for the associated channel to be set.
7. All modules set to 8, 9, 10 or 11-bit PWM mode use the same cycle length setting.
associated pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0).
channel is accessed via addresses PCA0CPHn and PCA0CPLn.
Operational Mode
Table 28.2. PCA0CPM and PCA0PWM Bit Settings for
PCA0 Capture/Compare Modules
Rev. 1.2
X X 1 0 0 0 0 A 0 X B XXX
X X 0 1 0 0 0 A 0 X B XXX
X X 1 1 0 0 0 A 0 X B XXX
X C 0 0 1 0 0 A 0 X B XXX
X C 0 0 1 1 0 A 0 X B XXX
X C 0 0 0 1 1 A 0 X B XXX
7 6 5 4 3 2 1 0 7 6 5
0 C 0 0 E 0 1 A 0 X B XXX
0 C 0 0 E 0 1 A D X B XXX
0 C 0 0 E 0 1 A D X B XXX
0 C 0 0 E 0 1 A D X B XXX
1 C 0 0 E 0 1 A 0 X B XXX
PCA0CPMn
C8051F58x/F59x
PCA0PWM
4–2 1–0
XX
XX
XX
XX
XX
XX
XX
00
01
10
11
315