C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 323

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

Note that the 8-bit offset held in PCA0CPH5 is compared to the upper byte of the 16-bit PCA0 counter.
This offset value is the number of PCA0L overflows before a reset. Up to 256 PCA0 clocks may pass
before the first PCA0L overflow occurs, depending on the value of the PCA0L when the update is per-
formed. The total offset is then given (in PCA0 clocks) by Equation 28.5, where PCA0L is the value of the
PCA0L register at the time of the update.
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH5 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF5 flag (PCA0CN.5) while the WDT is
enabled.
28.4.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:






Disable the WDT by writing a 0 to the WDTE bit.
Select the desired PCA0 clock source (with the CPS2 – CPS0 bits).
Load PCA0CPL5 with the desired WDT update offset value.
Configure the PCA0 Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
Enable the WDT by setting the WDTE bit to 1.
Reset the WDT timer by writing to PCA0CPH5.
PCA0CPL5
C
D
L
I
W
D
T
E
PCA0MD
W
D
C
K
L
PCA0CPH2
C
P
S
2
Figure 28.11. PCA0 Module 5 with Watchdog Timer Enabled
Write to
C
P
S
1
Equation 28.5. Watchdog Timer Offset in PCA0 Clocks
C
P
S
0
E
C
F
Offset
8-bit Adder
=
Enable
Adder

256
x
Enable
PCA0CPL5
Rev. 1.2
PCA0CPH5
Comparator
PCA0H
8-bit

+

256 PCA0L
–
Match
C8051F58x/F59x
PCA0L Overflow

Reset
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