C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 154

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F58x/F59x
17.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0–), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying
Comparator0 as the reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this
reset.
17.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA0) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “28.4. Watchdog Timer Mode” on
page 322; the WDT is enabled and clocked by SYSCLK/12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 1. The state of the RST pin is unaffected by this reset.
17.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
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The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
17.8. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
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A Flash write or erase is attempted above user code space. This occurs when PSWE is set to 1 and a
MOVX write operation targets an address above address 0xFBFF in Bank 3 on C8051F580/1/2/3/8/9 or
any address in Bank 3 on C8051F584/5/6/7-F590/1 devices.
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an
address above address 0xFBFF in Bank 3 on C8051F580/1/2/3/8/9 or any address in Bank 3 on
C8051F584/5/6/7-F590/1 devices.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above 0xFBFF in Bank 3 on C8051F580/1/2/3/8/9 or any address in Bank 3 on
C8051F584/5/6/7-F590/1 devices.
A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
“15.3. Security Options” on page 140).
A Flash read, write, or erase is attempted when the VDD Monitor is not enabled to the high threshold
and set as a reset source
Rev. 1.2