C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 18

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F58x/F59x
1. System Overview
C8051F58x/F59x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features
are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.

















With an on-chip Voltage Regulator, Power-On Reset and V
tor, the C8051F58x/F59x devices are truly stand-alone System-on-a-Chip solutions. The Flash memory
can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades
of the 8051 firmware. User software has complete control of all peripherals, and may individually shut
down any or all peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with-
out occupying package pins.
The devices are specified for 1.8 V to 5.25 V operation over the automotive temperature range (–40 to
+125 °C). The Port I/O and RST pins can interface to 5 V logic by setting the VIO pin to 5 V. The
C8051F580/1/4/5 devices are available in 48-pin QFP and QFN packages, and the C8051F588/9-F590/1
devices are available in a 40-pin QFN package, and the C8051F582/3/6/7 devices are available in 32-pin
QFP and QFN packages. All package options are lead-free and RoHS compliant. See Table 2.1 for order-
ing information. Block diagrams are included in Figure 1.1 and Figure 1.3.
18
High-speed pipelined 8051-compatible microcontroller core (up to 50 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
Controller Area Network (CAN 2.0B) Controller with 32 message objects, each with its own indentifier
mask (C8051F580/2/4/6/8-F590)
LIN 2.1 peripheral (fully backwards compatible, master and slave modes) (C8051F580/2/4/6/8-F590)
True 12-bit 200 ksps 32-channel single-ended ADC with analog multiplexer
Precision programmable 24 MHz internal oscillator that is within ±0.5% across the temperature range
and for VDD voltages greater than or equal to the on-chip voltage regulator minimum output at the low
setting. The oscillator is within +1.0% for VDD voltages below this minimum output setting.
On-chip Clock Multiplier to reach up to 50 MHz
128 kB (C8051F580/1/2/3/8/9) or 96 kB (C8051F584/5/6/7-F590/1) of on-chip Flash memory
8448 bytes of on-chip RAM
SMBus/I2C, Two Enhanced UARTs, and Enhanced SPI serial interfaces implemented in hardware
Six general-purpose 16-bit timers
External Data Memory Interface (C8051F580/1/4/5) with 64 kB address space
Two Programmable Counter/Timer Array (PCA) modules with six capture/compare modules each and
one with a Watchdog Timer function
Three Voltage Comparators
On-chip Voltage Regulator
On-chip Power-On Reset, V
40, 33 or 25 Port I/O (5 V push-pull)
DD
Monitor, and Temperature Sensor
Rev. 1.2
DD
monitors, Watchdog Timer, and clock oscilla-