C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 151

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

17.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
increases (V
power-on and V
cause the device to be released from reset before V
1 ms, the power-on reset delay (T
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V
power-on reset.
RST
. A delay occurs before the device is released from reset; the delay decreases as the V
DD
Logic HIGH
Logic LOW
DD
ramp time is defined as how fast V
2.45
2.25
2.0
1.0
monitor reset timing. The maximum V
Figure 17.2. Power-On and V
/RST
V
RST
PORDelay
Power-On
Reset
) is typically less than 0.3 ms.
T
PORDelay
Rev. 1.2
DD
DD
DD
reaches the V
ramps from 0 V to V
DD
Monitor Reset Timing
ramp time is 1 ms; slower ramp times may
Monitor
Reset
VDD
RST
C8051F58x/F59x
DD
level. For ramp times less than
monitor is enabled following a
RST
). Figure 17.2. plots the
VDD
DD
t
settles above
DD
ramp time
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