C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 261

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C8051F581-IMR

Manufacturer Part Number
C8051F581-IMR
Description
8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F581-IMR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
SFR Definition 24.3. SBUF0: Serial (UART0) Port Data Buffer
SFR Address = 0x99; SFR Page = 0x00
SFR Definition 24.4. SBCON0: UART0 Baud Rate Generator Control
SFR Address = 0xAB; SFR Page = 0x0F
Name
Reset
Name Reserved
Reset
Bit
7:0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB).
Bit
5:2
1:0 SB0PS[1:0] Baud Rate Prescaler Select.
Type
Type
7
6
Bit
Bit
Reserved
Reserved
SB0RUN
Name
Name
R/W
7
0
7
0
This SFR accesses two registers; a transmit shift register and a receive latch register.
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
Read = 0b; Must Write 0b;
Baud Rate Generator Enable.
0: Baud Rate Generator disabled. UART0 will not function.
1: Baud Rate Generator enabled.
Read = 0000b; Must Write = 0000b;
00: Prescaler = 12.
01: Prescaler = 4.
10: Prescaler = 48.
11: Prescaler = 1.
SB0RUN
R/W
6
0
6
0
Reserved
R/W
5
0
5
0
Reserved
R/W
Rev. 1.2
4
0
4
0
SBUF0[7:0]
R/W
Function
Function
Reserved
R/W
3
0
3
0
Reserved
C8051F58x/F59x
R/W
2
0
2
0
1
0
1
0
SB0PS[1:0]
R/W
0
0
0
0
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