C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 332

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F58x/F59x
29.1. PCA1 Counter/Timer
The 16-bit PCA1 counter/timer consists of two 8-bit SFRs: PCA1L and PCA1H. PCA1H is the high byte
(MSB) of the 16-bit counter/timer and PCA1L is the low byte (LSB). Reading PCA1L automatically latches
the value of PCA1H into a “snapshot” register; the following PCA1H read accesses this “snapshot” register.
Reading the PCA1L Register first guarantees an accurate reading of the entire 16-bit PCA1 counter.
Reading PCA1H or PCA1L does not disturb the counter operation. The CPS12 – CPS10 bits in the
PCA1MD register select the timebase for the counter/timer as shown in Table 29.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF1) in PCA1MD is
set to logic 1 and an interrupt request is generated if CF1 interrupts are enabled. Setting the ECF1 bit in
PCA1MD to logic 1 enables the CF1 flag to generate an interrupt request. The CF1 bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by soft-
ware. Clearing the CIDL1 bit in the PCA1MD register allows the PCA1 to continue normal operation while
the CPU is in Idle mode.
332
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI1
SYSCLK
External Clock/8
SYSCLK
External Clock/8
*Note: External oscillator source divided by 8 is synchronized with the system clock.
CPS12
0
0
0
0
1
1
1
1
C
D
L
1
I
PCA1MD
CPS11
C
P
S
1
2
000
001
010
011
100
101
110
111
C
P
S
1
1
0
0
1
1
0
0
1
1
C
P
S
1
0
C
E
F
1
Figure 29.2. PCA1 Counter/Timer Block Diagram
CPS10
IDLE
Table 29.1. PCA1 Timebase Input Options
C
F
1
0
1
0
1
0
1
0
1
C
R
1
PCA1CN
C
C
F
1
1
C
C
F
1
0
C
C
F
9
System clock divided by 12.
System clock divided by 4.
Timer 0 overflow.
High-to-low transitions on ECI1 (max rate = system clock
divided by 4).
System clock.
External oscillator source divided by 8.
Timer 4 Overflow.
Timer 5 Overflow.
C
C
F
8
C
C
F
7
C
C
F
6
0
1
Rev. 1.2
PCA1L
read
Snapshot
Register
PCA1H
Timebase
PCA1L
*
To SFR Bus
To PCA1 Modules
Overflow
CF1
To PCA1 Interrupt System