C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 321

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

28.3.6. 16-Bit Pulse Width Modulator Mode
A PCA0 module may also be operated in 16-Bit PWM mode. 16-bit PWM mode is independent of the other
(8/9/10/11-bit) PWM modes. In this mode, the 16-bit capture/compare module defines the number of PCA0
clocks for the low time of the PWM signal. When the PCA0 counter matches the module contents, the out-
put on CEXn is asserted high; when the 16-bit counter overflows, CEXn is asserted low. To output a vary-
ing duty cycle, new value writes should be synchronized with PCA0 CCFn match interrupts. 16-Bit PWM
Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a vary-
ing duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize the
capture/compare register writes. If the MATn bit is set to 1, the CCFn flag for the module will be set each
time a 16-bit comparator match (rising edge) occurs. The CF flag in PCA0CN can be used to detect the
overflow (falling edge). The duty cycle for 16-Bit PWM Mode is given by Equation 28.4.
Important Note About Capture/Compare Registers : When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Using Equation 28.4, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
PCA0CPLn
Write to
Reset
PCA0CPHn
Write to
0
ENB
ENB
1
Figure 28.9. PCA0 9, 10 and 11-Bit PWM Mode Diagram
W
M
P
0
1
6
n
E
C
O
M
n
PCA0CPMn
C
A
P
P
n
0 0 x 0
C
A
P
N
n
M
A
T
n
O
G
T
n
Equation 28.4. 16-Bit PWM Duty Cycle
W
M
P
n
E
C
C
F
n
x
Duty Cycle
PCA0 Timebase
ARSEL = 1
ARSEL = 0
R/W when
R/W when
Enable
N-bit Comparator
=
(Capture/Compare)
PCA0CPH:Ln
PCA0CPH:Ln
(Auto-Reload)
(right-justified)
(right-justified)
Rev. 1.2

-------------------------------------------------------- -
PCA0H:L
65536 PCA0CPn
65536
–
Overflow of N
match
th
R
A
S
E
L
Bit

C8051F58x/F59x
O
S
R
PCA0PWM
E
C
V
C
O
V
F
x
CLR
SET
Q
Q
C
S
E
L
L
1
CEXn
C
L
S
E
L
0
Set “N” bits:
01 = 9 bits
10 = 10 bits
11 = 11 bits
Crossbar
Port I/O
321