C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 224

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F58x/F59x
LIN Register Definition 21.6. LIN0ST: LIN0 Status Register
Indirect Address = 0x09
224
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
WAKEUP
ACTIVE
ERROR
ABORT
DTREQ
LININT
DONE
Name
ACTIVE
IDLT
R
7
0
LIN Active Indicator Bit.
0: No transmission activity detected on the LIN bus.
1: Transmission activity detected on the LIN bus.
Bus Idle Timeout Bit. (slave mode only)
0: The bus has not been idle for four seconds.
1: No bus activity has been detected for four seconds, but the bus is not yet in Sleep
mode.
Aborted Transmission Bit. (slave mode only)
0: The current transmission has not been interrupted or stopped. This bit is reset to 0
after receiving a SYNCH BREAK that does not interrupt a pending transmission.
1: New SYNCH BREAK detected before the end of the last transmission or the STOP
bit (LIN0CTRL.7) has been set.
Data Request Bit. (slave mode only)
0: Data identifier has not been received.
1: Data identifier has been received.
Interrupt Request Bit.
0: An interrupt is not pending. This bit is cleared by setting RSTINT (LIN0CTRL.3)
1: There is a pending LIN0 interrupt.
Communication Error Bit.
0: No error has been detected. This bit is cleared by setting RSTERR (LIN0CTRL.2)
1: An error has been detected.
Wakeup Bit.
0: A wakeup signal is not being transmitted and has not been received.
1: A wakeup signal is being transmitted or has been received
Transmission Complete Bit.
0: A transmission is not in progress or has not been started. This bit is cleared at the
start of a transmission.
1: The current transmission is complete.
IDLTOUT
R
6
0
ABORT
R
5
0
DTREQ
Rev. 1.2
R
4
0
Function
LININT
R
3
0
ERROR
R
2
0
WAKEUP
R
1
0
DONE
R
0
0