C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 316

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C8051F581-IMR

Manufacturer Part Number
C8051F581-IMR
Description
8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F581-IMR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
C8051F58x/F59x
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
28.3.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA0 counter/timer value is compared to the module's 16-bit capture/com-
pare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn regis-
ter enables Software Timer mode.
Important Note About Capture/Compare Registers : When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
316
Port I/O
hardware.
Crossbar
CEXn
Figure 28.4. PCA0 Capture Mode Diagram
W
M
P
1
6
n
x
PCA0CPMn
C
O
M
E
n
x
C
A
P
P
n
Rev. 1.2
C
N
A
P
n
0
1
M
A
T
n
0 0 0 x
O
G
T
n
W
M
P
n
C
C
E
F
n
0
1
C
F
C
R
PCA0CN
C
C
F
5
C
C
F
4
C
C
F
3
PCA0
Timebase
C
C
F
2
C
C
F
1
C
C
F
0
PCA0 Interrupt
Capture
PCA0CPLn
PCA0L
PCA0CPHn
PCA0H

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