C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 152

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F58x/F59x
17.2. Power-Fail Reset/V
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 17.2). When V
to a level above V
memory contents are not altered by the power-fail reset, it is impossible to determine if V
the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the V
V
monitor must be enabled to the higher setting (VDMLVL = 1) and selected as a reset source if soft-
ware contains routines which erase or write Flash memory. If the V
set to the high level, any erase or write performed on Flash memory will cause a Flash Error device
reset.
Important Note: If the V
is selected as a reset source. Selecting the V
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V
state is as follows:
1. Enable the V
2. If necessary, wait for the V
3. Select the V
See Figure 17.2 for V
monitor reset. See Table 5.4 for complete electrical characteristics of the V
Note: The output of the internal voltage regulator is calibrated by the MCU immediately after any reset event. The
When programming the Flash in-system, the V
highest system reliability, the time the V
(e.g., setting the V
changing it back to the low threshold setting immediately after the Flash write operation).
152
DD
Note: This delay should be omitted if software contains routines that erase or write Flash
memory.
monitor will still be disabled after the reset. To protect the integrity of Flash contents, the V
output of the un-calibrated internal regulator could be below the high threshold setting of the VDD Monitor. If
this is the case and the VDD Monitor is set to the high threshold setting and if the MCU receives a non-power
on reset (POR), the MCU will remain in reset until a POR occurs (i.e., V
A POR will force the VDD Monitor to the low threshold setting which is guaranteed to be below the un-
calibrated output of the internal regulator. The device will then exit reset and resume normal operation. It is for
this reason Silicon Labs strongly recommends that the V
(i.e. default value upon POR).
DD
DD
RST
monitor as a reset source (PORSF bit in RSTSRC = 1).
DD
monitor (VDMEN bit in VDM0CN = 1).
, the CIP-51 will be released from the reset state. Note that even though internal data
Monitor to the high threshold setting just before the Flash write operation and then
DD
DD
monitor timing; note that the power-on-reset delay is not incurred after a V
monitor is being turned on from a disabled state, it should be enabled before it
DD
DD
monitor to stabilize (see Table 5.4 for the V
DD
Monitor
monitor is disabled by code and a software reset is performed, the
DD
DD
Monitor is set to the high threshold setting should be minimized
monitor and configuring it as a reset source from a disabled
DD
DD
Rev. 1.2
monitor as a reset source before it is enabled and stabi-
Monitor must be set to the high threshold setting. For the
DD
Monitor is always left in the low threshold setting
DD
to drop below V
DD
Monitor will keep the device in reset).
DD
DD
DD
monitor is not enabled and
monitor.
Monitor turn-on time).
RST
, the power supply
DD
dropped below
DD
returns
DD
DD
DD