C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 339

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

29.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes
Each module can be used independently to generate a pulse width modulated (PWM) output on its associ-
ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA1 counter/timer, and
the setting of the PWM cycle length (8, 9, 10 or 11-bits). For backwards-compatibility with the 8-bit PWM
mode available on other devices, the 8-bit PWM mode operates slightly different than 9, 10 and 11-bit
PWM modes. It is important to note that all channels configured for 8/9/10/11-bit PWM mode will use
the same cycle length. It is not possible to configure one channel for 8-bit PWM mode and another for 11-
bit mode (for example). However, other PCA1 channels can be configured to Pin Capture, High-Speed
Output, Software Timer, Frequency Output, or 16-bit PWM mode independently.
29.3.5.1. 8-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA1CPLn cap-
ture/compare register. When the value in the low byte of the PCA1 counter/timer (PCA1L) is equal to the
value in PCA1CPLn, the output on the CEXn pin will be set. When the count value in PCA1L overflows, the
CEXn output will be reset (see Figure 29.8). Also, when the counter/timer low byte (PCA1L) overflows from
0xFF to 0x00, PCA1CPLn is reloaded automatically with the value stored in the module’s capture/compare
high byte (PCA1CPHn) without software intervention. Setting the ECOM1n and PWM1n bits in the
PCA1CPMn register, and setting the CLSEL1 bits in register PCA1PWM to 00b enables 8-Bit Pulse Width
Modulator mode. If the MAT1n bit is set to 1, the CCFn flag for the module will be set each time an 8-bit
comparator match (rising edge) occurs. The COVF1 flag in PCA1PWM can be used to detect the overflow
(falling edge), which will occur every 256 PCA1 clock cycles. The duty cycle for 8-Bit PWM Mode is given
in Equation 29.2.
Important Note About Capture/Compare Registers : When writing a 16-bit value to the PCA1 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA1CPLn clears the
ECOM1n bit to 0; writing to PCA1CPHn sets ECOM1n to 1.
Using Equation 29.2, the largest duty cycle is 100% (PCA1CPHn = 0), and the smallest duty cycle is
0.39% (PCA1CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOM1n bit to 0.
Equation 29.2. 8-Bit PWM Duty Cycle
Duty Cycle
=
Rev. 1.2

------------------------------------------------------ -
256 PCA0CPHn
–
256

C8051F58x/F59x
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