C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 54

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C8051F581-IMR

Manufacturer Part Number
C8051F581-IMR
Description
8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F581-IMR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
C8051F58x/F59x
6. 12-Bit ADC (ADC0)
The ADC0 on the C8051F58x/F59x consists of an analog multiplexer (AMUX0) with 35/28 total input selec-
tions and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated track-and-hold,
programmable window detector, programmable attenuation (1:2), and hardware accumulator. The ADC0
subsystem has a special Burst Mode which can automatically enable ADC0, capture and accumulate sam-
ples, then place ADC0 in a low power shutdown mode without CPU intervention. The AMUX0, data con-
version modes, and window detector are all configurable under software control via the Special Function
Registers shows in Figure 6.1. ADC0 inputs are single-ended and may be configured to measure P0.0-
P3.7, the Temperature Sensor output, V
is selected as described in Section “7. Temperature Sensor” on page 74. ADC0 is enabled when the
AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1, or when performing conversions in
Burst Mode. ADC0 is in low power shutdown when AD0EN is logic 0 and no Burst Mode conversions are
taking place.
54
*Available on 48-pin and
40-pin packages
P3.1*
P3.7*
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
Temp Sensor
GND
VDD
AMUX0
35-to-1
Figure 6.1. ADC0 Functional Block Diagram
ADC0GNH
ADC0MX
25 MHz Max
Burst Mode
Oscillator
Selectable
Gain
ADC0GNL
Conversion
SYSCLK
DD
Start
, or GND with respect to GND. The voltage reference for ADC0
ADC0GNA
Burst Mode
ADC0TK
Rev. 1.2
Logic
ADC0CF
ADC
12-Bit
SAR
ADC0GTH ADC0GTL
ADC0LTH
VDD
ADC0CN
ADC0LTL
Conversion
Start
01
00
10
11
32
Accumulator
AD0WINT
Compare
AD0BUSY (W)
Timer 1 Overflow
CNVSTR Input
Timer 2 Overflow
Window
Logic

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