C8051F581-IMR Silicon Labs, C8051F581-IMR Datasheet - Page 252

• Manufacturer Part Number: C8051F581-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F581-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F58x/F59x
252
Values Read
1110
1100 0 0 0 A master data or address byte
1000 1 0 X A master data byte was
0 0 X A master START was gener-
0 0 1 A master data or address byte
Current SMbus State
ated.
was transmitted; NACK
received.
was transmitted; ACK
received.
received; ACK requested.
Table 23.4. SMBus Status Decoding
Rev. 1.2
Typical Response Options
Load slave address + R/W into
SMB0DAT.
Set STA to restart transfer.
Abort transfer.
Load next data byte into
SMB0DAT.
End transfer with STOP.
End transfer with STOP and start
another transfer.
Send repeated START.
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT).
Acknowledge received byte;
Read SMB0DAT.
Send NACK to indicate last byte,
and send STOP.
Send NACK to indicate last byte,
and send STOP followed by
START.
Send ACK followed by repeated
START.
Send NACK to indicate last byte,
and send repeated START.
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
Values to
Write
0 0 X 1100
1 0 X
0 1 X
0 0 X 1100
0 1 X
1 1 X
1 0 X
0 0 X 1000
0 0 1
0 1 0
1 1 0
1 0 1
1 0 0
0 0 1
0 0 0
1000
1100
1100
1110
1110
1110
1110
1110
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