IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 104

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

6–6
Figure 6–4. Completed SignalTap II Design
Turning On the SignalTap II Option in Signal Compiler
DSP Builder Standard Blockset User Guide
2. Click the text under the block icon in your model and change the block instance
3. Add a SignalTap II Node block between the AND_Gate2 block and the
4. Add a SignalTap II Node block between the Eightbit Counter block and
5. Click Save on the File menu.
When you add node blocks to signals, each block implicitly connects to the
SignalTap II logic analyzer. This connection is a functional change to your model and
you must recompile your design before you can use the SignalTap II logic analyzer.
To compile your design, follow these steps:
1. Double-click the Signal Compiler block and click the SignalTap II tab in the
2. Verify that the Enable SignalTap II option is on.
name by deleting the text and typing the new text firstandout.
OR_Gate block and name it secondandout.
the Comparator block and name it cntout.
Signal Compiler dialog box.
When this option is on, Signal Compiler inserts an instance of the SignalTap II
logic analyzer into your design.
Preliminary
Chapter 6: Performing SignalTap II Logic Analysis
© June 2010 Altera Corporation
SignalTap II Example Designs