IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 214

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–6
Table 2–9. Comparator Block I/O Formats (Part 2 of 2)
Figure 2–3. Comparator Block Example
Counter
Table 2–10. Counter Block Inputs and Outputs
Table 2–11. Counter Block Parameters (Part 1 of 2)
DSP Builder Standard Blockset Libraries
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
data
sload
sset
updown
clk_ena
ena
sclr
q
Bus Type
[number of bits].[]
I/O
Signal
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
O1
[L].[R]
[1]
Table
Simulink (2),
Name
is an input port. O1
2–9:
Input
Input
Input
Input
Input
Input
Input
Output
Direction
(3)
Figure 2–3
The Counter block is an up/down counter. For each cycle, the counter increments or
decrements its output by the smallest amount that DSP Builder can represent with the
selected bus type.
Table 2–10
Table 2–11
Signed Integer, Unsigned
Integer, Signed Fractional
>= 0 (Parameterizable)
[L].[R]
Optional parallel data input.
Optional synchronous load signal.
Optional synchronous set port. (Loads the specified constant value into the counter.)
Optional direction (1 = up; 0 = down).
Optional clock enable. (Disables counting and sload, sset, sclr signals.)
Optional counter enable. (Disables counting but not sload, sset, and sclr signals.)
Optional synchronous clear. (Loads zero into the counter.)
Result.
O1: out STD_LOGIC
is an output port.
shows the Counter block parameters.
Value
shows an example with the Comparator block.
shows the Counter block inputs and outputs.
The bus number format that you want to use for the counter.
Specify the number of bits to the left of the binary point.
Preliminary
(Note 1)
VHDL
Description
Description
© June 2010 Altera Corporation
Chapter 2: Arithmetic Library
Implicit
Type
(4)
Counter