IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 215

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Arithmetic Library
Counter
Table 2–11. Counter Block Parameters (Part 2 of 2)
Table 2–12. Counter Block I/O Formats
© June 2010 Altera Corporation
[].[number of bits]
Use Modulo
Count Modulo
Specify Clock
Clock
Counter Direction
Use Synchronous
Load Ports
Use Synchronous Set
Port
Set Value
Use Clock Enable Port
Use Counter Enable
Port
Use Synchronous
Clear Port
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
I4
I5
I6
O1
[L].[R]
[L].[R]]
[1]
[1]
[1]
[1]
[1]
[L].[R]
Table
Simulink (2),
Name
is an input port. O1
2–12:
(3)
Table 2–12
>= 0 (Parameterizable)
On or Off
User defined
(Parameterizable)
On or Off
User defined
Increment, Decrement, Use
Direction Port (updown)
On or Off
On or Off
User defined
On or Off
On or Off
On or Off
[L].[R]
I1: in STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
I2: in STD_LOGIC
I3: in STD_LOGIC
I4: in STD_LOGIC
I5: in STD_LOGIC
I6: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
is an output port.
Value
shows the Counter block I/O formats.
(Note 1)
Turn on to enable the Count Modulo parameter. This option is not
Specify the clock signal name.
Specify the constant value loaded when the design uses the sset
Specify the number of bits to the right of the binary point. This field
is ignored unless Signed Fractional selected.
available for bit widths greater than 31.
Specify the maximum count plus 1. This represents the number of
unique states in the counter’s cycle.
Turn on to explicitly specify the clock name.
The direction you want to count or specify the direction with the
direction input.
Turn on to use the synchronous load inputs (data, sload).
Turn on to use the synchronous set input (sset). This option is not
available for bit widths greater than 31.
input. This value must be less than the Count Modulo value (if used).
Turn on to use the clock enable input (clk_ena).
Turn on to use the counter enable input (ena).
Turn on to use the synchronous clear input (sclr).
Preliminary
VHDL
Description
DSP Builder Standard Blockset Libraries
Explicit
Explicit
Type
(4)
2–7