IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 270
IPTR-DSPBUILDER
Manufacturer Part Number
IPTR-DSPBUILDER
Description
DSP BUILDER SOFTWARE
Manufacturer
Altera
Type
DSPr
Specifications of IPTR-DSPBUILDER
Function
DSP Builder
License
Renewal License
Software Application
IP CORE, DSP BUILDER
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
Not applicable / Not applicable
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4–8
Table 4–12. Decoder Block I/O Formats
Figure 4–4. Decoder Block Example
Demultiplexer
DSP Builder Standard Blockset Libraries
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
O1
[L].[R]
[L1].[R1]
[1].[0]
Table
Simulink (2),
is an input port. O1
4–12:
Table 4–12
Figure 4–4
The Demultiplexer block is a 1-to-n demultiplexer that uses full encoded binary
values. The value of the input d is output to the selected output. All other outputs
remain constant.
The sel input is an unsigned integer bus.
Table 4–13
Table 4–13. Demultiplexer Block Inputs and Outputs
(3)
d
sel
ena
sclr
0–(n-1)
[L].[R]
Signal
is an output port.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
O1: in STD_LOGIC
shows the Decoder block I/O formats.
shows an example with the Decoder block.
shows the Demultiplexer block inputs and outputs.
(Note 1)
Input
Input
Input
Input
Output
Direction
Preliminary
Data input port.
Select control port.
Optional clock enable port.
Optional synchronous clear port.
Output ports.
VHDL
Description
Chapter 4: Gate & Control Library
© June 2010 Altera Corporation
Demultiplexer
Type
Explicit
Explicit
(4)
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