IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 350

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

9–10
FIFO Buffer
Table 9–14. FIFO Block Parameters
DSP Builder Standard Blockset Libraries
Number of Words in
the FIFO
Data Type
[number of bits].[]
[].[number of bits]
Memory Block Type
Use Synchronous
Clear Port
Implement FIFO with
logic Cells Only
Use Show-Ahead
Mode of Read Request
Name
1
The FIFO block implements a parameterized, single-clock FIFO buffer.
Reading an empty FIFO buffer may give unknown (X) in hardware.
Table 9–13
Table 9–13. FIFO Block Inputs and Outputs
Table 9–14
d
wrreq Input
rreq
sclr
q
full
empty Output
usdw
Signal
User Defined
(Parameterizable)
Inferred,
Signed Integer,
Signed Fractional,
Unsigned Integer
>= 0
(Parameterizable)
>= 0
(Parameterizable)
AUTO, M512, M4K,
M9K, MLAB, M144K
On or Off
On or Off
On or Off
Value
Direction
Input
Input
Input
Output
Output
Output
shows the FIFO block inputs and outputs.
shows the FIFO block parameters.
Data input to the FIFO buffer.
Write request control. The d[] port is written to the FIFO buffer.
Read request control. The oldest data in the FIFO buffer goes to the q[] port.
Optional synchronous clear port that flushes the FIFO.
Data output from the FIFO buffer.
Indicates that the FIFO buffer is full and disables the wrreq port.
Indicates that the FIFO buffer is empty and disables the rreq port.
Indicates the number of words that are in the FIFO buffer.
Specify how many words you want in the FIFO buffer. The default is 64.
The data input type format.
Specify the number of bits stored on the left side of the binary point
including the sign bit.
Specify the number of bits stored on the right side of the binary point. This
option applies only to signed fractional.
The RAM block type. Some memory types are not available for all device
types.
Turn on to use the synchronous clear port (sclr).
Turn on to implement the FIFO buffer with logic cells only.
Turn on to use the show-ahead mode of read-request.
Preliminary
Description
Description
© June 2010 Altera Corporation
Chapter 9: Storage Library
FIFO Buffer