IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 415

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Symbols
.hex file
.mdl file
.mdlxml file
.qar file
.qip file
A
Advanced blockset interoperability
alt_dspbuilder_createComponentLibrary
alt_dspbuilder_exportHDL command
alt_dspbuilder_refresh_hdlimport
alt_dspbuilder_refresh_megacore
alt_dspbuilder_refresh_user_library_blocks
alt_dspbuilder_setup_megacore
alt_dspbuilder_verifymodel
AltBus block
Altera Quartus II software
AltLab library
Arithmetic library
asynchronous clear signal
Automatic flow
Avalon-MM interface
Avalon-MM Master block
Avalon-MM Read FIFO block
Avalon-MM Slave block
Avalon-MM Write FIFO block
Avalon-ST interface
DSP Builder Handbook Volume 2: DSP Builder Standard Blockset
Create component library command
Update HDL command
Update MegaCore command
Update user libraries command
Setup MegaCore command
Comparision command
Integration with MATLAB
wiring
Features
FIFO walkthrough
Interface blocks walkthrough
Master block
Read FIFO
Slave block
SOPC Builder integration
Write FIFO
Features
Packet Format Converter
Packet formats
SOPC Builder integration
12–1
12–2
12–2
1–3
13–6
12–1
1–2
1–2
6–2
1–1
7–7
7–2
7–6
3–19
7–4
2–1
7–21
7–16
5–6
5–3
1–2
3–25
3–22
7–22
7–1
5–9
7–20
5–11
1–3
4–1
4–2
7–8
1–3
9–6
12–3
10–6
Preliminary
Avalon-ST Packet Format Converter block
Avalon-ST Sink block
Avalon-ST Source block
B
Barrel Shifter block
Binary Point Casting block
Binary to Seven Segments block
Bit Level Sum of Products block
Bit width design rule
Bitwise Logical Bus Operator block
Black box
Boards library
Bus Builder block
Bus Concatenation block
Bus Conversion block
Bus Probe (BP) block
Bus Splitter block
Butterfly block
C
Case Statement block
Clock
Clock block
Clock_Derived block
Clocking
Explicit
HDL import
Implicit
Subsystem Builder
Using HDL import
Using SubSystem Builder
Setting a derived clock
Setting the base clock
Assignment
Categories
Clock enable signal
Configuration parameters
Global reset
HDL simulation models
Multiple clock domains
Sampling period
Simulink simulation model
Single clock domain
Timing relationships
Using a PLL block
Walkthrough
Walkthrough
3–8
3–22
8–1
1–2
8–1
11–1
3–11
3–2
3–11
3–17
6–9
6–5
2–2
3–8
1–2
3–4
1–3
4–5
8–1
8–6
5–18
6–8
3–14
8–1
3–8
5–20
3–8
6–7
3–18
2–2
© June 2010 Altera Corporation
6–4
2–2
3–9
3–16
8–1
2–3
3–16
4–2
2–3
4–3
Index
5–12