IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 383

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 11: Boards Library
Cyclone III EP3C120 DSP Board
Figure 11–8. HSMC Design Example for the Cyclone III EP3C120 DSP Board Blocks
Setting Up the Mezzanine Card Test Designs
© June 2010 Altera Corporation
1
Figure 11–8
The test design for the daughtercard connected to HSMC port B is very similar.
The required pin and clock assignments are already set up in the design examples. If
necessary, you can set up your own test design as follows:
1. The following Quartus II Global project assignments must be set with the value
2. Assign signals to the output enable pins for both channels of the analog-to-digital
3. Assign signals to the SPI bus interface signals for the chip in static mode
“Use AS REGULAR I/O”:
■
■
■
These assignments enable you to use the programmer pins as I/O.
converters (A2D1_OEB and A2D2_OEB) and tie them to GND.
(ADA_SPI_CSB and ADA_SPI_CSB) and tie them to VCC. When these signal are
pulled high, set the following signals:
AD_SCLK:
■
■
AD_SDIO:
■
■
RESERVE_DATA1_AFTER_CONFIGURATION
CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION
RESERVE_DCLK_AFTER_CONFIGURATION
High: Two’s complement output (for FIR or similar)
Low: Straight binary from near midrange
High: Duty cycle stabilizer (DCS) enabled to lower jitter
Low: DSC disabled
shows the test design for the daughtercard connected to HSMC port A.
Preliminary
DSP Builder Standard Blockset Libraries
11–9