IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 252

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–6
Complex Conjugate
Table 3–8. Complex Conjugate Block Parameters
Table 3–9. Complex Conjugate Block I/O Formats
DSP Builder Standard Blockset Libraries
Operation
Register Inputs
Use Enable Port
Use Asynchronous Clear Port
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
O1
1.[R1])
[L].[R]
Real([L1].[R1])Imag([L1].[R1])
[1]
[1]
Real([L1] + 1.[R1])Imag([L1] +
Table
is an input port. O1
Simulink (2),
Name
3–9:
The Complex Conjugate block outputs a fixed-point complex conjugate value by
performing simple arithmetic operations on the complex inputs. The operation can
optionally be conjugate, negative, or negative conjugate. For an input w = x + iy, the
block returns:
■
■
■
Table 3–7
Table 3–7. Complex Conjugate Block Inputs and Outputs
Table 3–8
Table 3–9
w
ena
aclr
c
(3)
[L].[R]
Conjugate: x – iy
Negative: –x – iy
Negative Conjugate: –x + iy
Signal
is an output port.
Conjugate, Negative,
Negative Conjugate
On or Off
On or Off
On or Off
shows the Complex Conjugate block inputs and outputs.
shows the Complex Conjugate block parameters.
shows the Complex Conjugate block I/O formats.
I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
I2: in STD_LOGIC
I3: in STD_LOGIC
O1Real: in STD_LOGIC_VECTOR({LP1 + RP1} DOWNTO 0)
O1Imag: in STD_LOGIC_VECTOR({LP1 + RP1} DOWNTO 0)
Value
Input
Input
Input
Output
Direction
(Note 1)
Specify the operation to perform.
Turn on to register the inputs and to enable the optional clock enable
and asynchronous clear options.
Turn on to use the clock enable input (ena).
Turn on to use the asynchronous clear input (aclr).
Preliminary
Complex inputs.
Optional clock enable.
Optional asynchronous clear.
Fixed point complex conjugate output.
VHDL
Description
Description
Chapter 3: Complex Type Library
© June 2010 Altera Corporation
Complex Conjugate
Implicit
Implicit
Implicit
Implicit
Type
(4)