IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 224

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–16
Table 2–23. Gain Block Parameters
Table 2–24. Gain Block I/O Formats (Part 1 of 2)
DSP Builder Standard Blockset Libraries
Gain Value
Map Gain Value to Bus Type
[Gain value number of bits].[] >= 0
[].[Gain value number of bits] >= 0
Number of Pipeline Stages
Clock Phase Selection
Use Enable Port
Use Asynchronous Clear Port On or Off
Use LPM
I
I/O
I1[
I2
I3
[1]
[1]
L1].[R1]
Simulink (2),
Name
(3)
Table 2–23
Table 2–24
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I2: in STD_LOGIC
I3: in STD_LOGIC
User Defined
Signed Integer,
Signed Fractional,
Unsigned Integer
(Parameterizable)
(Parameterizable)
>= 0
(Parameterizable)
User Defined
On or Off
On or Off
shows the Gain block parameters.
shows the Gain block I/O formats.
Value
(Note 1)
Specify the gain value you want to use as a decimal number (or an
expression that evaluates to a decimal number). The gain is masked to
the number format (bus type) you select.
The bus number format you want to use for the gain value.
Specify the number of bits to the left of the binary point, including the
sign bit.
Specify the number of bits to the right of the binary point. This option
applies only to signed fractional formats.
The number of pipeline delay stages. The Clock Phase Selection and
Optional Ports options are available only if the block is registered (that
is, if the number of pipeline stages is greater than or equal to 1).
Specify the phase selection with a binary string, where a 1 indicates the
phase in which the block is enabled. For example:
Turn on to use the clock enable input (ena).
Turn on to use the asynchronous clear input (aclr).
This parameter is for synthesis.
When on, the Gain block is mapped to the LPM_MULT library of
parameterized modules (LPM) function and the VHDL synthesis tool
uses the Altera LPM_MULT implementation.
1—The block is always enabled and captures all data passing
through the block (sampled at the rate 1).
10—The block is enabled every other phase and every other data
(sampled at the rate 1) passes through.
0100—The block is enabled on the second phase of and only the
second data of (sampled at the rate 1) passes through. That is, the
data on phases 1, 3, and 4 do not pass through the block.
Preliminary
VHDL
Description
© June 2010 Altera Corporation
Chapter 2: Arithmetic Library
Implicit
Type
(4)
Gain