IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 51

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Design Rules and Procedures
Bit Width Design Rule
Figure 3–6. 3-Tap Filter with BusConversion to Control Bit Widths
© June 2010 Altera Corporation
1
The following options can change the internal bit width resolution and therefore
change the size of the hardware required to perform the function that Simulink
describes:
■
■
■
Figure 3–6
widths.
In
is enabled in this example and shows that the inputs to the Delay blocks are of type
INT_8 but the outputs from the Bus Conversion blocks are of type INT_6.
You can also achieve bus conversion by inserting an AltBus, Round, or Saturate
block.
The RTL view illustrates the effect of this truncation. The parallel adder required has a
smaller bit width and the synthesis tool reduces the size of the multiplier to have a
9-bit output
Figure
Change the bit width of the input data.
Change the bit width of the output data. The VHDL synthesis tool removes any
unused logic.
Insert a Bus Conversion block to change the internal signal bit width.
3–6, the output of the Gain block has 4 bits removed. Port data type display
shows how you can use Bus Conversion blocks to control internal bit
(Figure
3–7).
Preliminary
DSP Builder Standard Blockset User Guide
3–7