IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 68

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–24
Displaying Port Data Types
Figure 3–22. Tutorial Example Showing Port Data Types and Pipeline Depth
Displaying the Pipeline Depth
Updating HDL Import Blocks
DSP Builder Standard Blockset User Guide
f
You can optionally display the Simulink and DSP Builder port data types for each of
the signals in your Simulink model by turning on Port Data Types in the Port/Signal
Displays section of the Simulink Format menu.
When you set this option, the DSP Builder internal signal type (SBF_L_R, INT_L,
UINT_L, or BIT where L, and R are the number of bit to the left and right of the binary
point) displays. For example, SBF_8_4 for a 12-bit signed binary fractional data type
with 4 fractional bits, or UINT_16 for a 16-bit unsigned integer.
Figure 3–22
enabled.
For more information about the DSP Builder internal signal types, refer to
“Fixed-Point Notation” on page
You can optionally display the pipeline depth on the primitive blocks (such as the
Arithmetic library blocks) in your Simulink model by adding a Display Pipeline
Depth block from the AltLab library.
You can change the display mode by double-clicking on the block. When set, the
current pipeline depth displays at the top right corner of each block that adds latency
to your design
Depth block symbol.
The HDL Import blocks in your design may need updating if you upgrade from a
previous software version or move a design to a different workstation.
shows the amplitude modulation example with port data type display
(Figure
3–22). The selected mode shows on the Display Pipeline
Preliminary
3–2.
Chapter 3: Design Rules and Procedures
© June 2010 Altera Corporation
Displaying Port Data Types