IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 53

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Design Rules and Procedures
Frequency Design Rules
Multiple Clock Domains
Figure 3–8. Example of Incorrect Usage: Mixed Sampling Rate on a NOT Block
© June 2010 Altera Corporation
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1
A DSP Builder model can operate using multiple Simulink sampling periods. You can
specify the clock domain in some DSP Builder block sources, such as the Counter
block. You can also specify the clock domain in DSP Builder rate change blocks such
as Tsamp.
When using multiple sampling periods, DSP Builder must associate each sampling
period to a physical clock domain that can be available from an FPGA PLL or a clock
input pin. Therefore, the top-level DSP Builder model must contain DSP Builder rate
change blocks such as PLL or Clock_Derived.
You can use a PLL block to synthesize additional clock signals from a reference clock
signal. These internal clock signals are multiples of the system clock frequency.
Refer to
If your design contains the PLL block, Clock or Clock_Derived blocks, the DSP
Builder registered blocks operate on the positive edge of one of the block’s output
clocks.
You must set a variable-step discrete solver in Simulink when you are using multiple
clock domains.
To ensure a proper hardware implementation of a DSP Builder design using multiple
clock domains, consider the following points:
■
■
Do not use DSP Builder combinational blocks for rate transitions to ensure that the
behavior of the DSP Builder Simulink model is identical to the generated RTL
representation.
Figure 3–8
Operator (NOT) block.
Two DSP Builder blocks can operate with two different sampling periods.
However for most DSP Builder blocks, the sampling period of each input port and
each output port must be identical.
Although this rule applies most of the DSP Builder blocks, there are some
exceptions such as the Dual-Clock FIFO block where the sampling period of the
read input port is expected to be different than the sampling period of the write
input port.
“Using the PLL Block” on page 3–14
illustrates an incorrect use of the DSP Builder Logical Bit
Preliminary
for more information.
DSP Builder Standard Blockset User Guide
3–9