IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 54

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–10
Figure 3–9. Data Toggling Faster than Clock
Figure 3–10. Stable Hardware Implementation
Using Clock and Clock_Derived Blocks
DSP Builder Standard Blockset User Guide
■
DSP Builder maps the Clock and Clock_Derived blocks to two hardware device
input pins; one for the clock input, and one for the reset input for the clock domain. A
design may contain zero or one Clock block and zero or more Clock_Derived
blocks.
If you use Clock_Derived blocks, and there is only one system clock, you must
generate an appropriate clock signal for connection to the hardware device input pins
for the derived clocks.
For a datapath using mixed clock domains, the design may require additional
register decoupling around the register that is between the domains.
This requirement is especially true when the source data rate is higher than the
destination register, in other words, when the data of a register is toggling at the
higher rate than the register’s clock pin
Figure 3–10
shows a stable hardware implementation.
Preliminary
(Figure
3–9).
Chapter 3: Design Rules and Procedures
© June 2010 Altera Corporation
Frequency Design Rules