IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 402

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

13–6
CIC Interpolation (3 Stages x75)
CIC Decimation (3 Stages x75)
Convolution Interleaver Deinterleaver
IIR Filter
32 Tap Serial FIR Filter
DSP Builder Standard Blockset Libraries
CIC (cascaded integrator and comb) structures are an economical way to implement
high sample rate conversion filters. This example implements a 3-stage interpolating
CIC filter with a rate change factor of 75, therefore, the output is 75 times faster than
the input. The design uses Stratix or Cyclone device PLLs. The input frequency is
2 MHz and the output is 150 MHz.
The example model is CiCInterpolator75.mdl.
CIC (cascaded integrator and comb) structures are an economical way to implement
high sample rate conversion filters. This example implements a 3-stage decimating
CIC filter with a rate change factor of 75, therefore, the output is 75 times slower than
the input. Use this design in digital down-conversion applications. The design uses
Stratix or Cyclone device PLLs. The input frequency is 150 MHz and the output is 2
MHz.
The example model is CicDecimator75.mdl.
Use convolution interleaver deinterleavers on the transmission side for forward error
correction. It provides an example of how the interleaver and deinterleaver work
together. The example uses a
The example model is top12x17.mdl.
This design example illustrates how to implement an order 2 IIR filter with a direct
form two structure. The coefficients compute with the MATLAB function butter,
which implements a Butterworth filter, with an order of two and a cutoff frequency of
0.4. This function creates floating-point coefficients, which are scaled in the design
with the
The example model is topiir.mdl.
This design example illustrates how to implement a low pass 32 tap FIR (finite
impulse response) filter with a 4-8 look-up table (LUT) for partial product
pre-computation. This design requires the Mathworks Signal Processing ToolBox to
calculate the coefficient with the FIR1 function:
FilterOrder = 32
InputBitWidth = 8
LowPassFreqBand = [0 0.1 0.2 1];
LowPassMagnBand = [1 0.9 0.0001 0.0001];
FlCoef =
CoefBitWidth = InputBitWidth +
ceil(log2((max(abs(FlCoef))/min(abs(FlCoef)))))
ScalingFactor = (2^(CoefBitWidth-1))-1;
FpCoef = fix(ScalingFactor * FlCoef);
Gain
block.
firls(FilterOrder,LowPassFreqBand,LowPassMagnBand);
Preliminary
Memory Delay
block for the interleaver FIFO buffers.
© June 2010 Altera Corporation
CIC Interpolation (3 Stages x75)
Chapter 13: Design Examples